Part Number: DAC3162EVM
I have the DAC3162EVM and the Xilinx AC701 (Xilinx Artix7 FPGA Eval Board).
The FMC connector on the DAC3162EVM and the AC701 are perfectly compatible. So I don't have any problems in connecting the two boards.
The DAC EVM Board has a TI device CDCP1803 on it. The CDCP1803 takes an external clock signal and provides the DAC Clk, FPGA Clk etc. I am able to give a 200 MHz external clock to the J9 connector of the DAC EVM and also able to tap and see the DAC Clk and FPGA Clk on the Oscilloscope. So far so good.
On the FMC connector of the DAC3162EVM, the FPGA Clk (From the DAC3162EVM board) is LVPECL standard. I have measured the voltages of this clock and found them to be as per the datasheet of the component CDCP1803 (The swing is from 1.5V to 2.5 V for either Clk_P or the Clk_N signals). This FPGA Clk will be the input clk to the FPGA and the DAC Data will be output w.r.t. this Clk. The FPGA Clk and the DAC Clk are set at same rate.
Now, whereas the Xilinx Artix7 FPGA doesn't support the LVPECL standard and the newer Xilinx FPGAs too don't support the LVPECL standard, I want to know which other standard can I select in my FPGA so that it can still take the FPGA Clk (LVPECL) to the Xilinx AC701 Board.
The DAC3162EVM Board has mapped/connected the FPGA Clk to the D19 and C19 pins of the Artix7 FPGA.
Waiting for your suggestion.
To me this appears to be a question for Xilinx. Is there something you need to know about the CDCP1803 output?
In reply to Jim Seton:
You are right. Actually my question was for both, TI and Xilinx. I am waiting for Xilinx to reply.
Out of the so many IO Standards supported by the Xilinx 7 series FPGAs I can't find anyone compatible with LVPECL as input.
I want to be very sure before I power ON the boards.
Finally, I feel that LVPECL output of the DAC3162EVM can not be given directly to Xilinx AC701 board through the FMC connector.
In reply to Jayant Patil:
You may be able to modify the FPGA_CLK output on the DAC3162EVM with some resistors to get the output to the correct LVDS level for the Xilinx device. See Figure 4 of the attached document.
interfacing diff standards.pdf
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