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Part Number: DAC3482
Dear to anyone who can help me out
I'm struggling with DAC3482 on my custom board for days, but all the trials have been found to be unsuccessful. The test conditions and the observed results are as follows.
1. Test conditions
1) Operational parameters
- Data clock : 100MHz
- DAC clock : 100MHz (External, no interpolation(1x) and NCO disabled)
- FIFO synchronization : Single sync source mode, all synchronous with non-periodic FRAME (dual mode also tested, but the result was the same)
- Data format : Word-wide
- Test input : Sine wave at the freq. of 100000000/1024Hz(=97.66kHz)
2) Register settings & configuration sequence
9 FIFO offset (properly chosen which doesn't issue the FIFO collision alarm)
32 0x2201 (and TXENABLE goes HIGH)
5 0x0000 (Loop the last 4 lines until any FIFO collision no longer occurs)
2. The results
1) Alarm FIFO 1 or 2 Away always occurring
2) The output waveform badly distorted (
3) Sawtooth shape periodic of 16 data clock cycles in the output observed
4) Pictures captured (Please look at the envelope but never mind the glitches since I think I can take care of them by adjusting clock phases later)
Thank you for your concerns!
I think I've finally solved it just by chance. I changed the interpolation factor 4x to 8x. What is the relation between DATA_CLK and DAC_CLK? I need 4x interpolation so I supplied 100MHz and 400MHz for DATA_CLK and DAC_CLK, respectively. Is there anything wrong with it? I don't understand how come it works if I set the interpolation factor to 8. Does DAC3482 use both rising and falling edges in processing signals?
In reply to HEUNGSUB SHIM:
Yes, the DAC3482 uses both rising and falling edges (DDR) of the DAC CLK.
In reply to Daniel Brock36:
When you say that your experiment "works" with 8x interpolation, are you meaningthat your output frequency is now much smoother? If so, 8x interpolation uses more filtering than 4x interpolation which may be why you see a much smoother output signal, but with your setup the output frequency would be incorrect. Are you also observing the correct output frequency?
In reply to Yusuf%20Agoro:
No, I didn't mean that the output was simply smoother. When I set the interpolation factor to 8x, the DAC3482 in my board started working correctly without any problem: neither distortion nor abnormal sawtooth envelope. What I don't understand though is why I set the interpolation factor to 8x, not 4x. I'm supplying 100MHz and 400MHz clocks as DATA_CLK and DAC_CLK, respectively, in the word-wide mode because I want to convert the frequency of the baseband signal to IF @125MHz and need a 4x interpolation. All the details involving the settings were provided in my 1st post. Is there anything wrong with what I have thought and done. However, the 4x interpolation ended up with abnormal behaviour. Once I changed the interpolation factor 4x to 8x, it suddenly started working. But why? If I look at the output signal before our IF saw filter, I have the fundamental IF signal at 125MHz and images, one of which shows at 275MHz. This is very strange to me because it is working as if the interpolation factor is 4x depite that it is currently set to 8x. If the interpolation factor 8x is valid, I should have supplied 800MHz as DAC_CLK, shouldn't I? In addition, our application is RADAR and DAC3482 is used to generate NLFM signals. I used to use DAC5687 followed by DAC5688. Both showed arbitrary phase impairments, unresolvable. That is why I migrated to DAC3482 and it is literally working fine in spite of the strange behaviour above that I don't understand. Thank you for your concerns, Yusuf.
So i looked into reproducing your register setup and I was unsuccessful. However, when testing interpolation 1x and 2x interpolation using Data Clock and Dac Clock rates in your setup everything worked fine for me.
So i am not sure what the issue is with the DAC3482 & your setup but as far as the relationship between Data clock and Dac clock, i found some information that may be useful.
Fifo out clock = DacClk/2/interpolation
This can be found on page 31 of the DAC3482 data sheet. If you do the math the FIFO out clock is half of the FIFO in clock. But the FIFO out clock should be reading twice as much data by design therefore the input and output rates remain consistent. it seems that in your setup you have to simulate the divide by two in the FIFO out clock equation by increasing your interpolation by a factor of two.
I'm grateful to your answer. However, the lines you highlighted are what I don't understand at all. As I said, my DAC3482 custom board is perfectly working with neither errors nor alarms involving FIFO. If so, the FIFO Out Clock rate should not be DACCLK/2/Interpolation but DACCLK/Interpolation*2 in my case because DATACLK and DACCLK are 100MHz and 400MHz respectively. But why should the interpolation factor be 8 not 4? The spectrum of the output looks like the interpolation factor is 4. I'd like to ask TI what they mean by interpolation. Is it somewhat different from that in the textbook?
You should never try the register settings that I attached in the 1st post because they won't work. The biggest change I made is the interpolation factor, 4 to 8, which cleared out all errors and FIFO alarms. But I don't know why. That is my question, still unsolved. The explanation you highlighted in the datasheet is rather confusing. To me, the register settings, the datasheet and the result do not seem to comply with one another. That is my conclusion after spending days, playing with my custom board. I'm very happy now because my 3482 board is perfectly working anyhow.
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