High Speed Data Converters Forum - Recent Threads

ADC5463 Evaluation Board PCB files

Stephen Machuzak — Mon, 17 Jun 2013 22:15:06 GMT

Hello,

I'm a student intern working for COSMIAC and we are designing CubeSats to detect lighting impulses in the atmosphere. We are using the ADS5463 in our design.

Are there any PCB files for the ADS5463 Evaluation Board? I need these to design the PCB on mentor graphics because the board we have is too big for our design.

Thanks!

TSW1400EVM CMOS interface

Alan Rothenberg — Tue, 18 Jun 2013 23:42:26 GMT

The product page for the TSW1400 EVM says that a CMOS interface will be supported in a future firmware upgrade. However, the technical documents and a TI sponsored You Tube video that I saw imply that the CMOS interface is working. Does anyone know if it is, or is the firmware upgrade still in the future?

TSW1400

Martin Althaus — Tue, 08 Jan 2013 17:23:51 GMT

Hello,

i use a TSW1400 with a TSW3085. Are there sample Files ( LTE GUI ) for the TSW1400 availible , such they exist for the TSW3100?

IN the High Speed DAte Converter Pro i can load some sample Files. But all sample Files have an offset from 30 Mhz to the LO. How can i create such Files?

When i create inthe Gui with " I/Q Multitone Genarator" some Signals i have always this 30 MHz offset. Or is the only way to use an offst -30 MHz from Carrier. My aim is to have a noisy or real LTE Signal in the adjacent Channel in the LTE enviroment.

Thanks for answers.

Martin

TSW1400EVB Source Code

David McGaw — Tue, 11 Jun 2013 13:49:48 GMT

Hello,

I am using a TSW1400EVB with ADS5400EVB to capture high-speed pulse data and need to modify the trigger algorithm on the TSW1400. Would you be able to send the source code? Thank you.

spurious at o/p of DAC3484

ram ela — Sat, 15 Jun 2013 09:16:57 GMT

I've made a board consisting of DAC3484, TRF3705 and LMK4806. DAC is runnig at 1.2 GSPS. At the o/p of TRF3705 I'm getting on & off spurious signals.

DAC3484 o/p is connected to TRF3705 with 300 MHz LC filter as given in TSW3084 evaluation board but i've not used transformer in between. I've found the clock to DAC and LO are clean.What may be the reason for this flickering spurs.

Ravi

ADC12D1800 Development board FPGA LVDS parllel interface code

Stephen Hinde — Tue, 18 Jun 2013 12:15:11 GMT

I was wondering if anyone could help me to understand why the ADC12D1x00 RFRB design package Verilog code has no IDELAY modules in it to vary the incoming data into the FPGA for the parallel interface? How does the design run at 900Mbps per LVDS pair with no compensation using the Xilinx IDELAY components available within the FPGA??

Thanks,

S Hinde.

LM97600 / about SYNC input

Ryuji Asaka — Wed, 05 Jun 2013 10:33:40 GMT

Hello,

Could you please kindly let me know about LM97600 SYNC function?

I have many question of LM97600. So I posted questions separately.

1. Training sequence

I think that training sequence is operated continuously during SYNC input is high in the data sheet Page 33 Serial Data Training Sequence.

Is my understanding correct ?

2.Sync timing

I think that SYNC is effective in both of Rising edge and Falling edge due to Figure4 and Figure5.

Is my understanging correct ?

3.syncrounous between SYNC and Fclk input

Should SYNC input be syncronized to Fclk input ?

4. meaning of "Multiple ADC Syncronization(data sheet Page 33)"

There is discription of "Multiple ADC Syncronization".

Is this mean multiple(2pcs or 3pcs or etc....) LM97600 use in one system ?

So, If I use one pcs of LM97600, I can ignore this information.

Is my understanding correct ?

Best Regards,

Ryuji Asaka

DAC3482EVM rework to support HSMC interface

Pete Harbour — Mon, 17 Jun 2013 20:58:32 GMT

Hello,

I am presenting a somewhat blind question, my apologies up front. Recently Kang Hsia helped me by arranging a rework of a DAC3482EVM digital bus connector to a connector that would support an HSMC interface to an Altera FPGA board. He suggested that I contact a colleague of his this week regarding this rework, but I do not have a specific individual's name. The factory DAC3482EVM has a Samtec QTH family connector with two mechanical mounting [retention] pins protruding from it (I assume these are designed to mate with the TI TSW family of boards). These pins will conflict with the connector on Altera FPGA development boards (Samtec QSH family, standard). Kang arranged a rework of a DAC3482EVM with a "standard" type QTH connector (QTH-090-01-L-D-A) without the -RT1 retention pin option.

Kang was working to have a 2nd board reworked for me this past week. He is on travel this week I understand. I wanted to ask if anyone is aware if he was able to get the rework process started; I believe the rework was done by TI or a TI partner.

Is there anyone I should specifically talk with about this?

Thanks,

Pete Harbour

adc08060

lin Michael — Mon, 17 Jun 2013 03:36:17 GMT

I use the ADC08060 for my data switch, use the typical circle, even I force the input to VDD or GND ,There is no output datas,not so much changes from the output.

Please Tell me why?

PICkit2 to ADC to serial

michael treanor — Wed, 12 Jun 2013 18:56:44 GMT

Hello there I am trying to program my PIC16F877 to recieve data from a rotary sensor. I am looking to create code for an ADC and send it out through a serial port to PuTTY. My code will compile ok but I am just not getting the signal out.

The code is attached

Please try to help me out. I am really stuck (Please visit the site to view this file)

DAC5675

Stan Vaughn1 — Fri, 24 May 2013 21:10:30 GMT

Hi,

we are testing a DAC5675 development board. We have set up the output for differential with 26 ohm resistors to +3.3V. We are driving the DAC board with a Xilinx SP601 development board and differential LVDS pairs. We have are generating a gaussian wave out of the DAC outputs (approximately 5 usec wide). However, the gaussian wave negative output has an amplitude of 1.0V while the positive amplitude is only 0.6V. What could cause this imbalance?

thanks!

Start Up Time For Analog to Digital Converters (ADC)

Darren O'Connor — Mon, 03 Jun 2013 15:36:12 GMT

Hello,

I have a low power, high-speed application in which I need to sample at 250 MHz and want to conserve power by shutting off the voltage to my ADC until there is a signal of interest. I'm wondering, with the ADS5444-SP and the ADS5463-SP, how long after the proper voltages are applied for supply power that the ADC samples will be correct? If your answer includes the pipeline delay for the devices, please indicate this is the case. If these parts have a start up time beyond 100 nS, are there any other space qualified parts capable of 250 MHz sample rates that have faster start up times?

Thanks in advance,

Darren O'Connor

Laboratory for Atmospheric and Space Physics at the University of Colorado, Boulder

LM97600 / Questions of Register

Ryuji Asaka — Wed, 05 Jun 2013 12:49:14 GMT

Hello,

Could you please kindly let me know about LM97600 register ?

I have multi questions of LM97600 . So I posted questions separately.

1..... Meaning Clock Bump of Bit1 of Register 01h (table 12)

Could you please kindly let me know about Clock Bump of Bit1 of Resister 01h ?

If I use one LM97600 only, I can ingnore this bit ?

2.....meaning Set tAD adjust of Bit0 of Register 01h (table 12)

Is this bit for adjustment of skew of each channels ADCs in one of the LM97600 ?

3.....Register 03h Bit11:6 (table 14)

In the Addr 03h of register, Bits 11:6 must be set to 00 0000b.

But, POR setting is 01 0110b.

Could you please kindly let me know correct setting ?

4....Register 0Ch Bits 9:5 and Bits 4:0 (table 23)

I think that Bits 9:5 and Bits 4:0 has five bits only.

But, these can setting 01d - 63d in data sheet.

Is this typo of 01d - 33d ?

If yes, correct delay is as below ?

Bits 9:5 , 0d= 0ps ,,,,,,,, 31d=155ps

Bits 4:0 , 0d=0ps ,,,,,,,,31d =12.4ps

5....Register 10h(table 27)

This regisrer is for Sync function and Sync function is for operating some pcs of LM97600.

So, I can set B15 to 0b as disable for one pc LM97600 using.

Is my understanding correct ?

6....Register 11h (table 28)

Could you please let me know the voltage of th e " Maximumum (tracks Vo) " ?

Best Regards,

Ryuji Asaka

[ADS41B29] how to use single input pin??

siwon kim — Thu, 13 Jun 2013 02:20:19 GMT

Hi I m now designing ADS41B29 circuit

The IC have pair input pin but I want to use single input pin

is it possible ?--

INP is signal input ,

INM is GND or 1.5V

LVDS Interface between ADS4125EVM and TSW1200EVM

Prashant Unch — Mon, 03 Jun 2013 10:45:20 GMT

Hi,

I am just trying to track the pins of FPGA used to interface with ADS4125EVEM.

I am surprisingly finding that, TRUE o/p of ADS4125 is connected to COMPLEMENT i/p of FPGA.

Example:

Differential ADS4125	ADS4125 Pin	Name	LVDS Connector Pin on ADS4125EVM	LVDS Connector Pin on TSW1200EVM	Name	FPGA Pin	Differential FPGA
True	38	D2-D3-P	76	76	Input9_M	F17	Complement
Complement	37	D2-D3-M	78	78	Input9_P	F16	True
True	5	CLKOUTP	56	56	DCLK_M	C20	Complement
Complement	4	CLKOUTM	58	58	DCLK_P	B19	True

If this is the connection then, I guess we need to invert the data before processing.

Am I going wrong somewhere ??

Regards

Prashant

DAC3482EVM question regarding HSMC data interface

Pete Harbour — Mon, 04 Mar 2013 22:19:59 GMT

Hi,

I am looking at the DAC3482EVM for a solution to interface with an Altera development board via HSMC. On the DAC3482EVM webpage there is a reference to the schematic/layout/BOM files of the DAC348xEVM (slrr002.zip). In that layout design I am looking at the HSMC mounting holes (the two holes on either end of J13) and notice that they are set with a 2.7" gap line in-between (referenced to the hole centers [ø 0.112"]). The standard mounting hole gap for HSMC is 2.80" in-line (ø 0.125"). Are these two mounting holes intended to provide a mechanical mount for the HSMC connector or is this data interface connector (J13) for something else? It's signals seem to map to the HSMC LVDS signals correctly so I am unsure what to make of the mounting hole mechanicals.

Thanks,

Pete

245.76 MHz Filter "FLT1" on the ADS62P49EVM

Stefan von der Mark — Tue, 31 Aug 2010 15:23:33 GMT

Hi,

I want to use the ADS62P49EVM with the onboard-clocking using the onboard CDCE72010 ("Clock Option 2" as described in section 2.2.4.2 of the User Guide).

For this configuration, I need a chrystal filter of 245.76 MHz, which unfortunately is not populated by default. The desing is obviously meant for a certain filter, as there is onboard matching and a certain footprint, however there is no hint in the documentation for specs of this filter other than the center frequency.

Can anyone give me a hint which filter I can use here?

Alternatively, I could use "Clock Option 3" using the LVPECL connection which does not need this filter. However, section 2.2.4.3 sais this option is "not recommended for SNR critical applications". Why is that so? What is the issue with this configuration? I have seen LVPECL connections between clock cleaners and ADC/DAC devices in many Appnotes, so this seems a quite common way to go.

Thanks for your help,

Stefan

Matlab for TSW1200 and ADS4229EVM

guan — Fri, 22 Jun 2012 09:01:16 GMT

Hello,

Is there a Matlab interface for the TSW1200 and ADS4229EVM? Could you advise me where can I download the Matlab code to interface to this ADC?
Another question, How many data can I capture in each channnel ?

Thanks,
Best Regards,
Guan Qing

Start Up Time and Input Signal Without Power Safety Questions

Darren O'Connor — Tue, 28 May 2013 22:38:57 GMT

Hello,

I am considering using the ADS5444-SP or the ADS5463-SP ADC converters in a space application. To limit power, I would like to power up the devices only when I have a signal event that I need to measure. While powered off, my first question is whether or not I can still have the clock and analog input signals be active without damaging or degrading the part? My 2nd question is how long after the power supply turns on will the device put out accurate data? I realize both parts have a data latency, which I am not concerned with. My question is really how long after the power supplies are settled can I expect to get good data out of the parts?

Thanks in advance, Darren

Update from DAC34H84 Evaluation Module RevD for Altera HSMC compatibility?

Andrew Do — Mon, 27 May 2013 04:29:11 GMT

Hello

In reference to Posted by Kang Hsia on Feb 13 2013 09:18 AM is there any plan to do another revision, or make an adapter board that will be compatible with the Altera HSMC connector? I note that the webpage for the DAC34H84 Evaluation Module still suggests that it is 100% compatible.

Thanks

Andrew

TSW3003 and TSW3100 EVMs

ABDEL MOUNAIM1 — Wed, 01 May 2013 16:32:53 GMT

Hi,
I use for the first time TSW3003 and TSW3100 EVMs. I want to know how to use to send data. I want advice on their configuration and the steps before each use. thank you :)

ADC12D1800RFRB noise level

Ethan wu — Wed, 05 Jun 2013 22:02:55 GMT

I have an ADC12D1800RFRB board. When I ground all input with 50 ohms terminators and calibrate ADC. I read background noise at the range of of 20 p-p (out of 4096), which basically take 5 bits precision away from the ADC. Is this the noise level I should expect.

ADC12D1600 default register values not as expected

Rob Sauk — Thu, 06 Jun 2013 21:25:10 GMT

Hi,

I was wondering what would happen if the reserved register (addr 0x8) does not come up with the power on default value of 0x0. For some reason, the power on default value is coming up as 0xFFFF. I am able to write 0x0 and change it to the default. This is the first time I've seen this issue. All other cards built with this chip have behaved as expected reserved register 0x8 = 0x0. All other registers are showing the correct power on reset values.

Has anyone else reported this as a problem? Will it be safe to just write 0x0 to this reserved register on power up and use it as normal?

Thanks for any advice.

Rob

clock input for ADS42LB69

jacky lu — Sun, 09 Jun 2013 03:21:04 GMT

SIR:

The ADS42LB69 clock input can be driven differentially with a sinewave, LVPECL or LVDS source. Which form of clock is best in performance?

Besides, some ADC of other company do not suggest the use of sinewave. Because the slew rate of sinewave is slower compared with LVPECL and LVDS, can ADS42LB69 work in best performance when providing sinewave clock?

Thank you!

Regards

Jacky

2013-06-09

ads4149 spi Interface

Fred L Skalka — Mon, 10 Jun 2013 15:19:59 GMT

I would like to daisy chain the SPI interface for four ADS4149 ADCs. When I disabel SEN, is the internal SPI interface put in bypass (i.e. SDIN is passed directly to SDOUT) or is the whole interface disabled (i.e. SDOUT is set to a default level regardless of the value of SDIN). Of course, this assumes that there is proper activity on SCLK.