Hi all, I use DAC5688 in software radio PCB design. It is connected and configured by a Xilinx Virtex 6 FPGA. I have some questions and would like to get some hints.For the clock modes, we would like to use External mode or PLL mode, such that only one pair of clock input is required. From the datasheet, it is cleared that In External mode, DAC output sample rate (fdac) is provided to CLK2/C.In PLL mode, an external reference clock is provided to CLK2/C, and uses the PLL multipler to obtain the high rate fdac. In datasheet, it is said that "The CLKO_CLK1 pin is configured as an output in this mode and will toggle at a required frequency for the configured interpolation rate and data mode." I know I can configure CLKO_CLK1 to be an output to drive the input data source (FPGA in my design) that sends the data to the DAC. The spec says CLKO max frequency is 160MHz.However, how can I set CLKO at a particular frequency? I read through the spec it does not find info saying how I can derive CLKO output from the CLK2/C.I would like to do the following:(a) In External mode, CLKO fdata would be a divided clock from the CLK2/C fdac.(b) In PLL mode, CLKO fdata is the same as the external reference clock source. Thank you for your advice.
Regards,Alex
Hi Alex,
You are correct that In both the external mode and PLL modes the CLKO will output the required DATACLK frequency for the configured interpolation and data input mode. The CLK1IN_ENA register in config2 will need to be set to "0" in both modes. The DAC5688's internal divider logic will automatically derive the CLKO from DAC's internal clock, so you cannot set CLKO at a other frequencies other than the one needed to latch in the data properly.
For instance, if the DAC output update rate is at 320MHz with 4x interpolation. The effective data rate is 80MSPS. The DAC will latch in data in SDR fashion.
1. With normal dual bus mode, the CLKO will toggle at 80MHz to latch in all 32-bits of I/Q data.
2. With interleaved bus mode, the CLKO will toggle at 160MHz (2x required to interleave) to latch in 16-bit of I/Q interleaved data.
3. With half-rate bus mode, the CLKO will toggle at 40MHz.
You can use this CLK0 as a reference to the FPGA and establish the required setup/hold time for the DAC's data input.
-KH