I want to clock data from ADS5282EVM to FPGA 3a DSP 3400 via FMC interface.
At this time i am using a DCM to produce two clocks (CLK0, CLK180), in order to clock the IDDR2 cell.
When i observe signals in Chipscope the LCLK that is fed to the DCM as an input has not the expected frequency depending on the frequency generator used to clock the ADS5282EVM. However the ADCLK has the expected frequency.
What maybe happening there?
Is the method with the DCM correct?
Can you advise me the appropriate method that i should use with this carrier board?
Can anyone suggest a methology for capture lvds ddr data in a Spartan 3a DSP3400 FPGA?
How does LCLK look like from Chipscope? Have you got any frequency error or something?
I hope you can find necessary information regarding this at the link below. Otherwise, you might have to consult Xilinx regarding this DCM issue.
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