Hi,
i am using DAC5688 with GC5016 in a digital filter.
Clock is 160MHz differential connected as on TSW4100 demo board.
Initialization sequence:
const u08 DAC_Ini[31] ={0x81, 0x0A, 0xE9, 0x00, 0x00, 0x92, 0x00, 0x00, // 0x92 -- 4-line interface 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0x10, 0x80, 0x00, 0x0D, 0xFF, 0x00, 0x39, 0x15};
unsigned char DAC_Init (unsigned char Dev){ u16 i; u08 Result; for (i = 1; i < 31; i++) WriteToDAC(Dev, i, DAC_Ini[i]); // DAC Sync WriteToDAC(Dev, 0x05, 0x92); // 1001 0010 WriteToDAC(Dev, 0x05, 0xB2); // 1011 0010 WriteToDAC(Dev, 0x05, 0x92); // 1001 0010 WriteToDAC(Dev, 0x16, 0x0); WriteToDAC(Dev, 0x17, 0x0); WriteToDAC(Dev, 0x05, 0xD2); // 1101 0010 WriteToDAC(Dev, 0x05, 0x92); // 1001 0010 for (i = 0; i < 3999; i++) continue; // delay reading Result = ReadDAC_PLL(Dev); return Result;} // DAC_InitIn a batch of about 100 boards(two DAC5688 on it) on one of the boards one DAC5688 starts on power up, but after put to sleep with:
void DAC_Sleep (unsigned char Dev){ WriteToDAC(Dev, 0x1A, 0x3E);}
newer wakes up.
On other board one DAC5688 (of two) newer starts. ReadDAC_PLL returns 0 all the time.
In both occasions DC voltage on the LPF pin is 0V and DC voltage on CLK0_CLK1 and LOCK_CLK1C is also 0V.
Normally voltage on filter pin is 1.2V and on clock inputs are around 1.5V.
Could the problem be because incorrect initialization or just chips are damaged?
Best regards,
Dmitri
Hi Dmitri,
I believe there are two issues.
The first is regarding the device synchronization. In your sequence, I did not see a command that issues the TXENABLE rising edge. Therefore, none of the logics may be synchronized correctly. I would recommend the following:
unsigned char DAC_Init (unsigned char Dev){ u16 i; u08 Result; for (i = 1; i < 31; i++) WriteToDAC(Dev, i, DAC_Ini[i]); // DAC Sync WriteToDAC(Dev, 0x16, 0x0); // set NCO block, QMC block, offset block to look for TXENABLE rising edge WriteToDAC(Dev, 0x17, 0x0); // set FIFO block to look for TXENABLE rising edge
WriteToDAC(Dev, 0x05, 0xB2); // 1011 0010 //set clock divider block to look for TXENABLE rising edge.
//apply TXENABLE rising edge here for (i = 0; i < 3999; i++) continue; // delay reading Result = ReadDAC_PLL(Dev); return Result;} // DAC_Init
Note: TXENABLE should be applied after all the logic blocks are ready for synchronization. TXENABLE also enables the DAC output at the same time. If you want to synchronize certain digital logics without disabling the output momentarily, you can use other sync functions such as hardware sync or software sync (via register 0x05)
Next, the synchronization sequence should not affect the biasing of CLK1/C pair. Since you are applying the clock1 pair externally, you may want to double check the clock driver to see if it is functioning properly. Also, it may be possible that the device may not be soldered down correctly. You may want to reflow the device and check again.
The device that could not wake up could also have the same soldering issue. Another possibility is that Channel B will go to sleep if Channel A is programmed to sleep regardless of the bit5, sleepb setting. It is possible that bit4, sleepa is still set active while you are checking for channel B output.
-KH