My hardware setup is currently a Xilinx SP605 evaluation board to TI FMC-DAC Adapter Rev D to TI DAC 3162 EVM Rev B.
Hi Julie,
I just want to clarify one comment first. You mention that you get an 8 mV swing on the FPGA clk line? Can you tell if its at the expected frequency?
Second, have you checked all outputs from the CDCP1803? Specifically, take a look at the Y0 outputs (R183 and R182) to see if these are swinging as expected. This is the clock line for the DAC.
Third, if there is a small (8 mV) swing on the FPGA clk lines, is it possible that the FPGA pins are set as output pins? This would cause a dual driver condition, where the FPGA tries to drive the lines one way and the clock chip tries to drive them a different way. One easy way to tell is measure the DC voltage at the clock chip output. It should be roughly around 3.3 / 2 V (1.65 V +- 0.5 V or so). If the clock output DC level is around 0 V or 3.3 V, then the FPGA is likely trying to drive these lines. You can also try to disconnect the adapter so that the clock chip sees an open circuit and see if the clock swings as expected.
Regards,Matt Guibord
Matt,
Thanks for the response. The 8mV swing does not look like the expected frequency. It really just looks like a slightly noisy line.
I checked outputs at 2 places -- the clock that goes to the FPGA and the clock that goes into the DAC (I think these are Y0 and Y1). I saw the same thing on both lines.
I double checked my constraints file and my top module in the FPGA code. The clock from the DAC are going in on "IN" ports.
Any other ideas?
Thanks,
Julie
I'm still looking for other ideas to get this DAC EVM board to work. What other suggestions can TI provide? Is there a way I can verify if this board is fried? All I know is that I've never seen white smoke, smelled any burning components, etc, but all other indicators point to it being defective.
It is getting the voltages that the CDCP1803 datasheet say are required. And, I'm sending in the 0.5Vrms, <500MHz signal. Beyond sending it a different clock signal, I'm not sure what to do. However, I don't want to send a clock signal that is out of spec and risk hurting the chip.
What should next steps be?
Regards,
Can you check the current draw from the 5 V power supply? Check it with and without the clock hooked up.
As a reference, here are the numbers from my EVM:Without Clock: 214 mAWith Clock (500 MHz): 224 mA
Disconnect all connections from the EVM, except 5 V power, when you're checking this to compare against mine. If your current draw is significantly different, there may be a problem. Please report back with your measurements.
When I'm sending a clock (and expecting a clock output), my 5V power supply shows current draw at 0.15 A.
I used JP2 to set the RESET signal going to the DAC to ground (always in reset). The power supply says that the board is drawing 0.11A now.
Julie,
I have received your shipping address from Marty Shank. We'll go ahead and ship out a new EVM to you that we have verified in our lab. This will be shipped out today. Please follow up with me after receiving the new board.
In the meantime, I forgot to ask you to first verify that the jumpers JP24, JP25, JP26, and JP27 are set to the LDO position, this will greatly vary the current measurement. The LDO setting gives us the most insight into whether the parts are drawing the right amount of current. Can you check this and report back whether it was configured with the LDOs or with the new current numbers?
Thanks for sending a new board. I'll let you know once it arrives and if I can get a clock through it. Is there something you'd prefer me to try before I attached to my SP605 and attempt to run the same clock through it?
Those 4 jumpers were set to DC-DC. The user manual said those were default, and I was getting voltages at all test points, so assume that was OK. I moved everything to LDO. I am seeing same results -- no clock output from CDCP.
With JP2 in not-reset (pins 1-2 shunted), I got 0.21 A. I was sending in a 0.5Vrms, 15MHz clock.
With JP2 in not-reset (pins 1-2 shunted), I got 0.22A when sending no clock.
With JP2 in reset (pins 2-3 shunted), I got 0.15 A.
Those current numbers look to be correct. All chips appear to be drawing the correct amount of power.
You said you probed at the clock chip input, was this on the side of C36 closest to the clock chip? Could you supply a screenshot?
Also, can you measure the DC voltages at the clock chip outputs?
When you get the board, I would suggest checking the clock chip outputs before plugging in the SP605 to verify that they are working correctly.
I received the new evaluation board this morning. I went through several check steps, but now have it attached to my SP605, feeding a clock generated by the SP605, and am seeing good clock output of the CDCP on both the scope and from chipscope. It appears that it was a hardware issue with the original board.
What do you want me to do with our original EVM board? May I keep the new EVM board that you sent so I can make progress, or do we need to send it back?
I'm glad everything is working now. I'm surprised a board got sent out without a working clock chip. We do test all boards before we stock them. It is possible it was damaged some time after testing due to ESD or phsyical handling.
Please keep the new board for your development. If you wouldn't mind, I would like to receive your original non-working board back, so I can try to fix it for future use in the lab. I'll send you an e-mail with my address.