I have a queation about the FMC ADC Adapter Card. I want to connect some High Speed ADC's to an SP605 eval Board from Xilinx. Will the Adaptor work with full functionality on an FMC LPC Connector (the SP605 only has an FMC LPC connector)?
Thank you in advance!
Can you please clarify which specific high-speed ADCs you are interested in? The answer to your question may be different depending upon the product.
thanks for the fast answer.The ADS58C48EVM or the ADS5282EVM (Or do you have some faster 8 Channel ADC's?) are my favorites right now.
The FMC adapter cards simply pass the LVDS clock and data pairs from the TI High Speed Data Converter EVM through to the FMC conenctor that Xilinx uses into their development platform. Either of those EVMs you mention should work well into the ML605 development platform.
One note about the use of the ADS5282 EVM, though. The DDR bit clock from the ADC EVM is routed to a global clock input, but the frame clock is not. Early revisions of the FMC adapter card had the frame clock routed to a clock input that could not be used as a data input. Which of the two routings you want would depend on how you plan to use the frame clock in your design. What *we* do with the frame clock is we use it as if it were just another data channel that happens to have a known data pattern so that we can key off that pattern and know where the msb and lsb are onthe other 8 data channels. In fact, frame clock even has the same setup and hold timing specs around the DDR bit clock as the other data pairs, and so we latch it into the FPGA using the bit clock. Thus we want the frame clock routed to a data pair, not a global clock input despite the presence of the word 'clock' in the name of the frame clock.
The ADS58C48 is a four channel device, and because the data format is parallel LVDS instead of serial, it uses a lot more pins on the connector, but the FMC adapter board routes them all over to the development platform.
Thanks for your detailed Answers Richard, but will it also work well on an SP606 Board? The ML605 has two FMC Connectors (HPC and LPC), but the SP605 only has one FMC LPC connector.
I read at http://www.xilinx.com/support/documentation/white_papers/wp315.pdf page 3
"The HPC and LPC connectors use the same mechanical connector. The only difference is which signals are actually populated. Thus, cards with LPC connectors can be plugged into HPC sites, and if properly designed, HPC cards can offer a subset of functionality when plugged into an LPC site."
So Im a bit affraid of the functionality of the card at my Board.
I do see now that you did mention the SP605 rather than the ML605 development platform in your first post. I do not know what potential differences there may be between the Xilinx development platforms for Virtex vs. Spartan. We do not have one of each development platform in hand for each family of device from each FPGA vendor. This would be a question for the FPGA vendor directly, I believe. A Xilinx representative actually picked the pin assignments of the FMC adapter card when we made the board, but with the ML605 in mind.
If you do have the SP605 in hand already, then you should have or should be able to get the mapping from the FMC connector to the FPGA itself. The physical design database (schematics) are available on the TI web for the TI EVMs and for the adapter board itself, so you can follow the signal assignments through the connectors to the FPGA. You would have to do this anyway before you could generate the constraint file for your development code. You'd mostly want to verify that the LVDS bit clock goes to a suitable clock input to the FPGA, and that all of the data bit LVDS pairs go to LVDS inputs of the FPGA. I have been told that the LVDS bit clock may not go to a global clock input of the Spartan, but I cannot verify that, and a global clock input may not be necessary if the clock input can still be used in a clock region that encompasses the LVDS inputs. There are hierarchies of clock inputs and clock buffers, I believe, such as global clock buffers and regional clock buffers, and the Xilinx design tools would tell you if the pin assignment that you end up with into the SP605 would work our not.
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