1.From the datasheet, i know that i can a 1:1 balun to drive the ADC in DESIQ Mode.
2.From the datasheet, i do not know which kind of balun i should select to drive the ADC in DESIQ Mode. Can i select a 1:1 balun to drive the ADC in DESCLKIQ Mode like in DESIQ Mode?
We have done a study on a few different input structures to drive the various DES Modes - and presented it at Tech Days 2011 in San Jose, CA. I have attached the pdf report here. Except for a very special application, we do not generally recommend using DESCLKIQ Mode because it is very difficult to drive. Consider DESIQ Mode instead for highest bandwidth.
Let me know if the report answers your questions - or if you have further questions.
0804.TI GSPS ADC Driving for High Bandwidth Applications.pdf
Hi Marjorie, Thanks for you reply, it is of great help .
From the ADC12D1X00 Reference Board-REFERENCE DESIGN which is provided by the TI.Some questions i cannot understand.1.Why the control singals(PDI、PDO...TPM) of the chip of ADC12D1600 connect a matching resisstor of 50ohm,and a matching resisstor of 10kohm is connect to the VIRTEX4 FPGA? If i use the virtex6 FPGA,can i delete the two resistors?2.The output of the LMX2531LQ1570E is "Fout". from the "REFERENCE DESIGN" the "Fout" is connect a RF-RELAY(the RF-RELAY has a funtion of select clock,is similar to a switch),and then connect a chip of B0430J50100A00. Can you provide the datasheet about the chip of RF303 how to work? Is the RF-RELAY a necessaries? Whether use the chip of RF303,it can improve some characters. Can i delete the chip of RF303, and directly connect the "Fout" to the chip of B0430J50100A00 ?
1. For the 10k ohm resistors, there are a couple reasons: 1) these nets may also be connected to VA or GND via a jumper and having a 10kohm resistor between the FPGA output driver and VA or GND protects the FPGA output driver and 2) in case there is any difference between the FPGA power supply and the ADC's VA, the 10kohm resistor also prevents too much current from being burned. The reason for the 50 ohm resistors, placed close to the ADC, is so that this resistor, in combination with the input capacitance of the input pin, can form a low-pass filter which protects the pin from accidentally switching in case the board trace picks up some noise.
If you simply replace the Virtex 4 with a Virtex 6, but use the same design / topology, then I recommend to leave the 50 ohm and 10k ohm resistors in the design, based on the reasons for their placement, as mentioned above.
2. I found a datasheet to the RF relay here:
If, in your design, you do not need access to an external clock source and plan to use just the LMX chip, you should delete the relay and connect the output from the LMX directly to the input of the balun (via the 10pF capacitor).
Hi Marjorie ,
Thanks for you reply!
The datasheet of RF303-5 you provided i had downloded, but i do not know how to works ! Thanks agian！
Before the ADC12D1600,i need a IF filter, its features:
1.Center frequency : 1.5GHz
2.1dB bandwidth : 600MHz
3.VSWR : <1.5:1
4. Delay fluctuations with group: 300MHz < 1ns
600MHz < 3ns
5.Fluctuations in the band : < 0.5dB
6.Of-band rejiection : > 30dB (f0+fi >300MHz)
> 40dB(f0+fi >660MHz)
Can you provide a chip with similar functions. Thanks!
I can recommend that you check at Mini-Circuits, Murata, Maa-com, Narda, or Microwave Filter Company.
I have a problem to consult you !
ADC12D1600 is a high speed A/D converter. If the input signal's frequency(VINI+/-,VINQ+/-) is 70MHz, and the sampling frequency is about 300M, relative to the chip of the ADC12D1600,the sampling frequency is low. Will it affect the performance of the chip ? I have the same question about DAC5670 .
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