Does anyone have idea, what might be the maximum spi instruction frequency for DAC3282? In other words, how long I should keep SDENB at high state, before I can initiate a new spi command to the DAC?
The maximum SCLK rate for all the registers except config5 is 100ns min (10MHz max). The SCLK rate for the config5 temperature register is 1us min (1MHz max). This register has to run at a slower rate due to the SCLK being the SAR ADC sample clock for the temperature sensor.
You are correct that the SDENB have to be de-asserted (go to 1) and then re-asserted (go to 0) for each SPI access. Designer excepts about 10 clock cycles of de-assertion. On our current EVM, our SDENB de-assertion time is about 8ms between each SPI access with the SCLK running at 500kHz. The SPI is still fast enough for some of the common controls and configurations.
To speed up SPI access, you can configure the instruction byte of the SPI access to write and read up to 4 registers at a time. You may refer to page 20 of the datasheet for more detail.
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