On page 18 of the ADS5463-SP datasheet it states that the DRY signal should be used to capture the DATA out of the ADC. However, when I look on page 9 of the datasheet and review the timing information it appears that the skew between the DATA and DRY can cauase set-up violations when trying to use DRY to capture the DATA. In my application I would like to use the IDDR primitive in a xilinx FPGA to capture the DDR data out of this ADC using the DRY as the capture clock- but based on the timing numbers it looks like that will not be a reliable approach across temperature and voltage variations. Am I mis-understanding the datasheet? Doe TI have any app notes on how to use DRY to capture the DATA?
Thanks for the help
Hi,
DRY is source-synchronous to the DATA/OVR which is aligned to the edge of DATA. You'll have to adjust phase delay around 90 degree to latch DATA from FPGA.In order to get the valid data window, you also have to consider "DATA to DRY skew" from -1250ps to +700ps at the edge of DATA. If sampling rate is 400MHz, period is 2.5ns while the period of DRY is 5ns.At the rate of 400MHz, the valid window of DRY is calculated as 3.05ns (= 5ns - 1.25ns - 0.7ns).
Thanks,
KW