Hello. two questions.
1. If I want to only use one pair of two output data clocks (pin H2/H1 and G2/G1) for both bus A and bus B, the only way is to clear the bit D3 or D4 of the register through SPI to disable one clock pair's output? Or we can think that any one of two output data clock (DACLKP/N or DBCLKP/N)) can be used for clocking both bus A and bus B, and logically no need to consider to disable that unused clock pair? My concering is, if we just use one pair of clock for both bus a and bus B, and all related PCB traces lengthed are aligned exactly, and connected to one FPGA at 400Mhz~500Mhz data rate, is there any timing issue? Or the safer way is keeping using two pairs of the clock respectively for bus A and bus B?
2. Currently, the PCB decal of ADS5407 (BGA-196) for PADS Layout is available? Or where can I find the PCB decal in TI website?
Thank you very much.
Jason
