Dear All,
Wishes for a prosperous new year ! (Better late than never... :) )
I have a rather simple question this time.
The FPGA sends 4 bytes at each go to the Cypress's data lines and from there to WV5.
In the Verilog code these bytes are : data_3, data_2, data_1, data_0; where 3 and 1 are set to zero (only 8 bits from the ADC).
(1) As it comes to be I need to use all 4 bytes for my application. When I try to send something else (i.e. set data_3 to 0F) this does not produce the expected result on the WV5 plot. I tried looking into the scripts but could not find anything. I also checked the scripts for the 12 bit devices. My guess is that WV5 never sends the address to read (data_3 and data_1).
(2) If (1) is true; Is there a way to trick WV5 into thinking I am using a 12 bit board ?
(3) Is there a way to setup the script so that one sample consists of two bytes instead of one ?
Thanks in advance,
Evros
