TSW14J56 EVM

Fabio,

The Altera device on theTSW14J56EVM is loaded everytime after power up using the HSDC Pro GUI. There is no factory installed firmware. If you load your own firmware, TI cannot guarantee a replacement if the board is damaged. We can provide you with the firmware if needed. What modifications are you attempting to do? This may be something we can assist you with.

Regards,

Jim  

Jim Seton,

Thanks for your answer,

I would like to use DSP on FPGA.

Hi Jim,

Can I use the USB interface on TSW14J56EVM and Quartus II to program the Altera device?

Thank you.

Fabio,

Could you clarify the exact configuration for the rbf file? For example, what should things like "Congiruation Scheme", "Generate Compressed Bitstream" etc be set to in the Quartus II "Device and Pin Options" "Configuration" tab be set to.

I've created one that should simply turn on some of the user LEDs, but not even the D28 (the config done) goes high. I download it with the HSDC tool and it seems to work, but nothing happens.

Also, it would be helpful to know the exact part number of the Altera GZ chip. The schematic does not include the speed grade.

Thanks

Sorry, meant to say "Jim" in previous post.

Answered my own question: after trying several combinations, turning off "Generate Compressed Bitstreams" did the trick.

The TSW14J56EVM board is a great tool to experiment with the JESD204b and I was able to generate output using your GUI pretty quickly. But I wish TI would understand that that is not the real purpose. The real goal is to create our own designs to talk to your DAC and ADC chips. Without more information on how to do that, the board is not really very useful.

David,

The full part number for the Altera device is 5AGZME1E3H29C4N. If you need firmware to help you with your design we can provide some examples, both Altera and Xilinx based. The main purpose of the TSW14J56 is to allow customers the capability to test our JESD204B EVM's. Many customers contact the FPGA vendors for support on how to interface to these ADC's and DAC's. We are currently working with both Altera and Xilinx on coming up with ways to help customers design these interfaces with app notes, sample firmware, ect... This is currently work in progress.

Regards,

Jim

Jim,

Thanks for the part number.

Both the Altera and Xilinx firmware examples would be very helpful. I'm currently trying to decide between the two.

Thanks,
Dave

Dave,

I am currently out of the country on business travel but will get you this firmware sometime next week when I return.

Regards,

Jim

Jim,

Thanks, that will be very helpful.

One more question: I'm using the opencore eval version of Altera's JESD204b megacore. It does not allow the creation of .rbf files (I had used those as you suggested to just blink LEDs). So I need to use the JTAG connector to directly program via the Quartus II Programmer. But will I still be able to read ADC samples from the onboard RAM via the USB cable? Or does moving the JTAG jumpers disable the USB altogether? From the schematic, it looks like the USB has multiple paths to the FPGA.

But if this is a problem, any thoughts on how to get around this?

Thanks,
Dave

Hi Dave,

Yes you can still read data from RAM even after moving the jumpers to use the JTAG connector. We have done this several times without any issues.

Thanks,

Eben.

Eben,

Thanks for the info.

I'm having trouble getting Quartus II to use the USB Blaster from Altera (not sure if it is ii). Moved the jumpers J4 to J7 and Win7 sees the cable, but the programmer does not see the FPGA. Is there anything else I need to do?

I had trouble installing the USB Blaster driver. The plug-n-play did not work and I had to manually install it.  

Thanks,

Dave 

Hi Jim,

I would also like to get the firmware example for Altera (Arria V). Would you be able to send it to me?

Thanks!

Turns out the JTAG connector is not keyed. Amazing ...

But it works now.

Jim,

Hope you got back safe. I'm having good luck with getting things working, but the firmware examples would really help.

For some reason DAC out A, C and D look fine, but B is noisy. They all look fine when I use the High Speed Data Converter Pro software, so it must be something I'm doing.

Thanks,
Dave 

Dave,

I am slowly catching up on all of my emails. Do you still need the firmware? If so, please provide me with the details again as I forgot what FPGA you are targeting.

Regards,

Jim

Jim,

No problem. I have a DAC working but am having trouble with the ADC and resets.

The DAC board is the TI DAC38J84EVM.

The ADC board is the TI ADS42JB69EVM

The FPGA board is the TI TSW14J56EVM which has an Altera 5AGZME1E3H29C4. I'm using the Altera Quartus II tools and JESD204b Megacore.

If you have FPGA code for a Xilinx ZC-706 or KC-705 board (or any other board) that would also be helpful. I never got the Xilinx JESD204b to work at all.

Thanks,
Dave 

Dave,

Xilinx has converted our firmware using the latest JESD IP with the latest version of Vivado. This should be available within the next 24 hours, which I will then pass on to you. The target FPGA is Kintex 705.

Regards,

Jim  

Jim,

That will be great.

Right now I'm mainly looking at Altera though (via your TSW14J56EVM). Any chance of getting that as well. I'm doing something wrong on the ADC resets and am not even sure I'm using the right clocks pins.

Thanks,
Dave

David,

This link will take you to the Altera firmware used on the TSW14J56. This is based off of the MTI JESD IP. We will have an Altera Megacore based JESD IP project availble in about 1 month.

Regards,

Jim

https://txn.box.com/s/xf8ekhsu98alyzxdirwe

Jim,

Thanks, that helps a bit. Could at least check pin outs.

I got the TI DAC to work in a day with the Altera core and naively thought the ADC would be just as easy, but no luck after a week of trying.  

Is the MTI core better? Every example I can find uses it instead of the Altera core.

Thanks,
Dave

Dave,

MTI core has been out for a little while thus the reason for more examples. Our MTI license expired so we will be doing all future projects with the Altera Megacore. We should have an ADC example ready in the very near future. Can you provide me with your email address so we can send the code as soon as it is available?

Regards,

Jim

Jim,

I really appreciate that. My email is hand@corestar-corp.com

Thanks,
Dave

Jim,

Any progress on the Altera Megacore version of the firmware?

Thanks,
Dave

Dan,

I will check with our engineer who is in charge of this development and either I or he will get back with you on this.

Regards,

Jim

Hi Jim!

I am also looking forward to this. For evaluation and prototyping, I have purhcased ADS42JB69EVM and TSW14J56EVM. A reference design would be quite helpful while implementing my own.

Pentti

Hi David, Pentti,

Please provide your email address so I can forward a reference design to you.

Thanks,

Eben.

Hello Eben!

Nice to hear from you!

My email is:

pentti@sankola.com

Thanks in advance :-)

Pentti

Hi Eben,

Mine is hand@corestar-corp.com and I'm using:

The DAC board is the TI DAC38J84EVM.

The ADC board is the TI ADS42JB69EVM

with Altera Megacore on the TSW14J56EVM

Thanbks,
Dave

Zhou,

You can download the firmware from the following link below.

Regards,

Jim

Zhou,

The file is 21Mbytes. I cannot email an attachment this big. Do you have a file transfer tool we can use?

Regards,

Jim

Junzhe,

Some of the last batch of TSW14J56 Rev B boards TI built had Arria V parts installed that were rated for 12.5Gbps. If you have a Rev B board, remove the fan and see if the FPGA is labeled as follows:  5AGZME1E2H29C3N. This part has transceivers rated at 12.5Gbps. If you have one of our newer Rev D boards, this is also rated at 12.5Gbps. If you have a Rev B board with the slower FPGA, we can exchange your board for a newer Rev D.

Regards,

Jim 

Hi Jim,

My friend has downloaded the file for me this morning.

Thank you very much for your help.

Best Regards,

ZHOU Yigang

Junzhe,

If you have a valid license, you should be able to compile the design. What version of Quartus are you using? What version of JESD204B license do you have? You will need Quartus version 15.0 and Altera IP-JESD204B Altera JES204B MegaCore

Regards,

Jim

Junzhe,

You may not have the latest firmware. Go the TSW14J56EVM product folder on the TI website and request the latest firmware.

Regards,

Jim

Jim,

I never found that I can download the firmware in the TI's website.Thank you for your advise.

Regards,

Junzhe Zheng

I got the same problem. My computer can see the JTAG cable, but in the programmer of quartus it says that "unable to scan device. Can't scan JTAG chain." 

I'm using TSW14J56EVM, and already moved the pins jp4 - jp7 in order to use JTAG to program the onboard FPGA.

I'm not able to convert the firmware provided on its website since I don't have the license to use some special IP core in it.

JTAG seems like the only way to do it.

Do you have more detail instruction for using JTAG to program the board?