Question about DAC908E of power on

Dear all

Can anyone respondvthe question?

I must answer the customer. I don't have much time.

Best regards,

Hi Shinichi,

This response is not unexpected. There are essentially three events happening here.

1. The DAC is powered on and the output latches assume some default value, which is undefined. So the startup scenario is expected.
2. The rising edge on the clock due to the FPGA config latches in the digital data presented at the data pins, either all 0's or all 1's, depending on when your data switches relative to the clock.
3. The DAC output updates with the new value on the clock falling edge that occurs at the end of the FPGA configuration.

In order to start the DAC with a default output, I believe they will need to hold the PD pin high during startup. Once the FPGA is configured, the data should be set to the desired starting condition and the clock should be run. After one clock cycle the latches should be updated and the PD pin can be set low to begin normal operation.

Secondly, I would suggest using the same load on both outputs. So if they have 60Ω on IOUTp, then IOUTn should also have 60Ω.

Regards,
Matt Guibord

Hello Matt,

Thank you so much for your information.
Shinichi-san caught a cold, so please allow me to respond of Shinichi-san.
And, please let me confirm your reply.

You meant the output is caused by latching default value which is undefined. So, the output value is undetermined for each device. Is this correct?

And, could you please tell me what is influenced when the using resistors aren't same on both outputs?

And, do we have the device which doesn't occur the happening.

Best Regards,
Nishimura Soichi

Hi Nishimura-san,

Correct, this is the default value being latched which is undefined. All of our DACs will have an undefined default. In order to control it, you must either shut the output down (PD) or use the TXENABLE feature available on some of our DACs. This DAC has the PD pin which can be used to keep the DAC output in a known state during startup.

Regards,
Matt Guibord

Hi Matt-san,

Thank you for your reply in detail.

Please tell me one more additional question. I want to confirm your workaround of power up order.

The workaround is PD pin high during startup. But, PD is specified as -0.3V to VD+0.3V in maximum rating. PD is needed to go to high after VD power on. So,The order is as VD power on, then PD goes high, then VA power on. Is this order is correct to not occur the issue of the customer?

Best Regards,

Nishimura Soichi

Hi Nishimura-san,

You're correct, that is going to be an issue. You would need a pull up resistor tied to VD to pull up the PD pin as the supply ramps. Whatever controls the PD pin (FPGA, uP) would need to be tri-stated during this process to avoid "overriding" the pull up resistor. Note that the PD pin has an internal pull down, which I'm guessing is around 100 kΩ based on the input current spec.

Regards,
Matt Guibord