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DAC34H84 on TSW30SH84 EVM Complex Mixer image cancellation

Christophe Quindroit
Prodigy 20 points
Other Parts Discussed in Thread: DAC34H84

Dear everyone,

I have a misunderstanding with the DAC 34H84. I am using the TSW30SH84 EVM. My setup is configured as follow:

Signal baseband BW Fs = 307.2MHz

DAC 34H84

Interpolation = 4

Sampling Frequency = 1288.8MHz

Complex Mixer NCO Frequency FNCO = 76.8MHz

LO frequency FLO = 1.9232GHz

So, I would like to transmit two bands centered at F1=9.6MHz (Fs/32) and 19.2MHz (Fs/16) at baseband level as depicted on figure 1.

By using the GUI, I am able to cancel the IQ imbalance (QMCxxx variable) and the DC offset (Offsetxxx variable).

Figure 2 shows the measurement of the RF output from the evaluation board.

On the right of the spectrum, you can observe the two bands that I want to transmit centered at FLO+FNCO+F1=2009.6GHz and FLO+FNCO+F2=2019.2MHz.

However, on the left side of the spectrum, you can observe two not desired “images” centered at FLO+FNCO-F1 and FLO+FNCO-F2.

Of course, I didn’t expect this output so do you know where does this images come from? Is it a bad configuration of the DAC or a problem with images coming from interpolation process?

 

Thanks a lot for the support.

 

Christophe

  • 0
    TI__Guru 66114 points

    Christophe,

    A couple thoughts:

    1. The NCO and the complex mixer require an initialization step before proper operation. The initialization signal is selected in register 0x1F. It will program the part to look for the signal. The most common way is to use the sif-sync signal to initialize the circuit. Without the initialization, it is possible to get the sideband on the first NCO/complex mixer upconversion.

    2. The input data to the DAC34H84 may not have perfect 90degree phase shift between the I/Q signal. These may be caused by the shift in input data latching of the rising/falling edge of clock. We have a customer latching in data off by one sample and this has caused enough for the I/Q imbalance. You may want to adjust the timing of your input data to double check. Check out the following post for some ideas:

    http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/329685.aspx

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 20 points

    Thanks Kang,

    The problem was a one sample delay between I/Q.

    So the problem is solved.

    Thank you for your support.

    Chris