AFE7222 - external pull up resistance and pull down resistance on LVDS pin

Hi Hirotaka,

Pull ups and Pull downs are not required for any of the LVDS input pins you listed.

100-ohms differential termination should be enough.

Thanks,

Eben.

Eben san,

Thank you for your prompt reply!

How about the fail-safe in case of open circuit?
We guess that it is required to set pull-up and pull-down to prevent open circuit?
Or, is the device included pull-up and pull-down?

Kind regards,

Hirotaka Matsumoto

Hirotaka,

The device does not include any pull-up or pull-downs internally.

In most applications the DAC inputs are constantly driven from an FPGA or DSP so open circuit is not a concern.

Use the app note below which talks about failsafe biasing of LVDS inputs as a guide if open circuits are a concern in your application.

http://www.ti.com/lit/an/snla051b/snla051b.pdf

Thanks,

Eben.

Hi Ebenezer San,

Thank you for your update!

<Q1>
In general, how much of pre-bias voltage is required? 25mV?
(Vidh and Vidl are 350mv, so it seems that differential noise margin is enough values)

<Q2>
About settings of Pin INN_B_ADC, INP_B_ADC, our cusomer use only 1CH.
How should non-use of INN_B_ADC, INP_B_ADC treat? 
Our cusotmer use 100Ω for terminator(terminal resistance).
Is this setting correct, or not?
And then, how should the setting of resister do? - is not required?

We need your help.

Kind regards,

Hirotaka Matsumoto

Hi Eben San,

We have additional question.

If we don't use Sync Pin, please teach us more details.
The datasheet shows that "Sync pin can be tied to ground.
(or in the case of differential SYNC input tie SYNCINP to logic low and SYNCINN to logic High)".

So, in the case of differential SYNC input,  should SYNCINP and SYNCINN tied with 100Ωterminal(terminal resitance ) or not?

Kind regards,

Hirotaka Matsumoto

Hi Hirotaka,

Vidl and Vidh are the maximum LVDS voltage swing.

First consider the TX_CHA_PDN or TX_CHB_PDN register bits if they can serve the same purpose as the failsafe bias resistors. When these register bits are set, the output of the DAC is forced to mid code.

If you are going to implement failsafe at the LVDS inputs then between 25mV to 50mV pre-bias voltage should be enough.

ADC input pins that are not used can be left un-connected. In your case since you are not using channel B, power down this channel through SPI.

There is no need for the 100ohm differential resistor for the SYNC pin. Just tie SYNCINP to LOW and SYNCINN to HIGH if unused.

Thanks,

Eben.

Hi Eben San

Thank you for your reply.

We'd like to ask word "mid-code".
The data sheet says "mid-code".
So, what does it mean?  It means middle voltage from grand level, or not?

Kind regards,

Hirotaka Matsumoto

HI Eben San,

Thank you for your prompt reply!

Kind regards,

Hirotaka Matsumoto