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About an initialization setup of DAC5687.

Satoshi
Guru 19485 points
Other Parts Discussed in Thread: DAC5687

Is it sometimes required about an initialization setup of DAC5687 in addition to the following register setup?

--------------------------------------------------------------------

[Register setup]
・CONFIG2:Write to 0x00

・CONFIG3:default (0x00)

--------------------------------------------------------------------

・Is it necessary to Write another register?
・When there is necessity, which register is set up?
・If there are other operations required for initialization, please let me know.

Thank you for your consideration.

  • 0
    Guru 19485 points

    How is a situation about the affair asked the other day?
     
    If it is sometimes checked with a customer in order to issue a reply, please let me know.

    Besr Regards,

    Satoshi

  • 0 in reply to Satoshi
    Guru 19485 points

    From a customer, when they wanted the early reply, there was a request.

    I became hurry and, excuse me, please advise me.

    Satoshi

  • 0 in reply to Satoshi
    TI__Guru 66004 points

    Satoshi-san,

     

    The use of these registers would depend on the end application needed by the customer. For instance, the customer may or may not want to use the NCO or complex mixer for their end application.

     

    If NCO, QMC, and coarse mixers are not needed, then config2 can be set to 0x00

     

    Normally, Config3 can be set as default unless the user requires 4 wire SPI. Config3 also need to be adjusted if the user need special input bus features such as half-rate and USB. DAC_ser_data and counter_mode(2:0) are not normally used unless we are in debugging phase.

     

    I would suggest a quick review with the customer regarding Table 1 and Figure29 to Figure 32 to see which blocks are needed in customer’s system. Based on their feedback, then a proper register map can be programmed.

     

    Best Regards,

    Kang Hsia

  • 0 in reply to Kang Hsia
    Guru 19485 points

    Dear Kang-san

    Thank you for the reply.

    A customer's register data is written to below.
    (The place changed from the default is extracted)

    Addr=0x00, Data=0x30
    Addr=0x01, Data=0x09
    Addr=0x02, Data=0x20
    Addr=0x03, Data=0x00
    Addr=0x0C, Data=0x00
    Addr=0x1C, Data=0x01
    Addr=0x17, Data=0x7F
    Addr=0x18, Data=0x7F
    Addr=0x19, Data=0x55

    ※I think that QMC/NCO/Mixer is disable.
    And,Addr=0x04 is not Write.

    As for the customer, FPGA is performing a serial setup and digital input of DAC5687.
    I checked that the Write processing by a serial is satisfactory, and that the input from FPGA to DAC had come out. It is in the situation out of which only the output of DAC has not come.

    If the timing of a Write has specification, please let me know.

    Moreover, if there is a mistake in a setup of a register, please let me know.

     

    Best regards,

    Satoshi

  • 0 in reply to Satoshi
    TI__Guru 66004 points

    Satoshi-san,

    some comments:

    0x00 = 0x30. The DAC is set up in HP/HP mode with x4L mode. Please make sure the input bandwidth and output bandwidth requirement in Table 9. Attached is the spreadsheet for customer to calculate frequency planning.

    0x01 = 0x09. x4L mode, FIFO bypassed, inv_pll_lock = 0, dual clock mode. Please make sure the timing between CLK1 and CLK2 are tightly controlled since the FIFO is not used to absorb phase offset between the two clocks. Follow table 2, 4th option for detail. I am assuming PLLVDD is 0V since PLL is not used at this point.

    0x02 = 0x20. dual clock mode, offset binary. Same guidance above.

    0x03 = 0x00 NCO off.

    0x0C = 0x00 - no need to write since NCO is off.

    0x1C = 0x01 - phstr_clkdvi_sel = 1. It is really a test mode. I don't see a harm programming this.

    0x17 to 0x19. Programming gain A and gain B

    Overall, I think the register settings are fine. Please ask the customer to double check the input/output bandwidth requirement. Also, please ask them to pull TXENABLE high after the registers are programmed to start the DAC transmission.

    -Kang

    DAC5687_dualrealIFmodes.xls