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DAC3171 lvds clock

Gabriele Gobbin
Prodigy 70 points
Other Parts Discussed in Thread: DAC3171, DAC3174

Hello Everybody!

In my company we are selecting the DAC for a new product. We are very interested in DAC3171 for its speed and precision. Anyway, initially we are going to make this device work to a lower speed than its maximum but I can not find any information about minimum working frequency of the LVDS interface and the relationship between DACCLK and DATACLK.

Does it have just a maximum frequency so it can work at a frequency as low as needed? Are there any reccomended relations to be respected between the two clocks (other than the obvious observation that if I write in a FIFO faster than I read it will overflow)?

 

Regards,

Gabriele Gobbin

  • 0
    TI__Mastermind 29220 points

    Hi,

    Since this device does not support interpolation, the data clock and the dac clock must be at the same rate.  (if there were 2x interpolation, then the data clock would be half of the dac clock, etc.)

    Since the DAC clock is expected to be a high quality clean, low-jitter clock, then the usual use case would be to supply that clean clock to the DACCLK and then supply a *copy* of that clock to the FPGA or ASIC to use for the digital interface, and then the FPGA could use that clock to supply a digital sample clock and sample data to the DAC.  The sample interface just needs to meet setup/hold timing into the DAC and the FIFO is there to decouple the data clock from the dac clock and not have to have any phase relationship requirements between the data clock adn DAC clock.   But the data clock *does* need to be from that same frequency reference as the DAC clock so that the FIFO does not eventually overflow or underflow. 

    So if you were to run the DAC at some slower sample rate than max such as 300Msps for example, then the DACCLK and the DATACLK would each be 300MHz.   The data clock would latch the sample data on the rising edge of the data clock.  The dual channel version of this device (DAC3174) would run the data clk at the same rate but would use rising *and* falling edges of the data clock to latch twice as many samples into the DAC for the two channels.

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Prodigy 70 points

    Hello,
    thanks for your reply. Well, it is quite clear that the two clocks must be at the same rate; good to know that there are not phase relationship requirements.
    Now, just to be sure about the frequency: are there any problems to make it work at even slower speed? For example, does it work good at a sample rate of about 80Msps? I think that there should not be any problem but I just want to be sure before asking my boss to spend some money on the dev kit.
    Thanks again,

    Regards,
    Gabriele Gobbin

  • 0 in reply to Gabriele Gobbin
    TI__Mastermind 29220 points

    Hi,

    There should be no problem running at a slower sample rate such as this.  There is no min sample rate listed in the datasheet and this device does not have a PLL that would have a min to max operating rate.

    Regards,

    Richard P.