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High Speed DAC DAC38J82IAAV SFDR value for 500MHz

Other Parts Discussed in Thread: DAC38J82

Hi,

I have choosen DAC38J82IAAV part DAC having 2.5Gbps maximum sampling rate and 12 bit resolution.

In data sheet the output SFDR mentioned is 67dBc for 230MHz.

I need to use a DAC of output 500MHz. What will be the SFDR for 500MHz output for Sampling frequency of 2.5Gsps.

Kindly provide the SFDR value of DAC37J82IAAV for 500MHz which is operating in a maximum speed of 1.6GHz.

Regards

Soumya

  • Hi Soumya,

    This information is included in the "Typical Characteristics" plots in the datasheet. Please see Figure 7. Note that the SFDR at this frequency will be limited heavily by HD2 and HD3, so frequency planning around those will allow you to achieve better SFDR within a smaller bandwidth.

    Regards,
    Matt Guibord

  • Hi Matt,

    Thank you for the reply.

    The SFDR verses output frequency graph is showing that : At Sampling frequency of 2.46Gsps & 500MHz DAC output, SFDR is greater than 60.
    So the sampling frequency of 2.46MHz shall be used for getting SFDR of 60 when Maximum DAC output range is 500MHz.

    Regards

    Soumya

  • Hi Soumya,

    Correct. And the SFDR at 2.5 Gsps will be the same. From 2.46 Gsps to 2.5 Gsps there won't be much difference in performance.

    Regards,
    Matt Guibord

  • Hi Matt,

    I am having one more doubt in the same DAC38J82 part.

    There are 2 PLL in this DAC. One for DAC clock & another for serdes clock.

    We need to decide the serdes clock output first and in the basis of this we need to calculate what reference clock we need to use for the serdes PLL.

    Let us consider I need to use x8 lanes, with a maximum serdes speed of 3.125Gbps.

    what should be my serdes clock ?

    Assumption 1:

    As per the <Table 3: Relationship Between Lane Rate and SerDes PLL Output Frequency>

    is it 1GHz as I am using the quarter rate

    Assumption 2:

    But as per the concept if i need to have a data rate of 3.125Gbp,

    then The serdes clock frequency * No of bit per clock = 3.125Gbps.

    As per <Table 2. Lane Rate Selection> the no of samples per serdes PLL clock is one i.e. 16bit.

    So the serdes clock frequency for achieving 3.125Gbps shall be = 3.125Gbps/16bit = 0.1953GHz.

    Which assumption is correct?

    Kindly suggest how to select the serdes PLL Clock output as per the Data rate.


    Regards

    Soumya

  • Hi Matt,

    I need to have some clarification for the SERDES PLL clock generation.

    I am using DAC38J82.

    SerDes Lane rate: 6Gbps.
    DACCLK: 1200MHz (From External PLL)

    As per the data sheet recommendation:

    For HALF RATE:
    The SerDes PLL frequency shall be 0.5 of the Lane rate.
    Refer <Table 3. Relationship Between Lane Rate and SerDes PLL Output Frequency> .

    I am going generate PLL reference clock of 200MHz from 1200MHz by writing 6 to <serdes_refclk_div> register.
    The PLL output frequency of 3000MHz shall be generated by writing 5 to the rw_cfgpll [8:1] (MPY) register.

    So I will get a clock of 3000MHz. Which is 0.5 of the lane rate(6Gbps).

    Please confirm if the above assumption is correct.

    Regards
    Soumya
  • Hi Soumya,

    Your numbers aren't quite working out. Start from the opposite side. If you need 3 GHz at the serdes PLL and your multiplier is 5, then you need a reference clock of 600 MHz. If the DACCLK is 1200 MHz, then the serdes_refclk_divider needs to be set to 2 (0001).

    Try using the DAC38J82 GUI (as mentioned in the other thread) to generate the appropriate configuration.

    Regards,
    Matt Guibord
  • Hi,

    Sorry for the inconvenience. I need to use a multiplier value of 15. Wrongly it has been mentioned as 5.

    So if I will have a PLL reference frequency of 200MHZ, then the PLL output frequency will be 200 * 15 = 3000MHZ.
    In this configuration multiplier value is higher.

    But Your recommendation is seems good.

    As per your configuration

    Divider value is 2 (PLL reference clock = 600MHz)
    Multiplier value is 5 (PLL output=3000MHz)

    I am going to use the a divider value of 2 & a multiplier value of 5 for a DACCLK of 1200MHZ.

    Please confirm if I am right.

    Regards
    Soumya
  • Hi Soumya,

    Yes, use my recommendation with a multiplier of 5. Typically the smallest multiplier is best from a jitter standpoint.

    Regards,
    Matt Guibord

  • Hi Matt,

    Thank you for your response.

    Regards

    Soumya

  • Hi,

    Can you able to provide the DAC register setting for the below configuration.

    1. x4 JESD204 serdes lanes
    2. x2 Interpolation
    3. 16 bit DAC resolution
    4. Sampling rate of 1.2Gsps
    4. A & D output channe
    5. JESD data rate of 6Gbps
    6. SerDes PLL clock of 1.5GHz (As want to use full data rate)

    Let me know If any other information is needed for setting the configuration.

    Regards
    Soumya