I am writing through the 3 pin configuration of the serial interface to the ADS5400 from a Virtex 5 FPGA. My question is to get a confirmation for the proper bit sequence for the instruction and write cycle of MSB 7 down to 0. I cannot seem to get a test pattern out of the chip and it keeps defaulting to normal operating mode (LVDS is outputting sampled data bits). When I wrote to Register 5, I was able to verify back that I wrote correctly within a INSTRUCTION & READ cycles. Do I need to keep the serial communication low after the write cycle is complete for the test pattern out to work?
The sequence I am sending for REGISTER 6 is:
Instruction cycle: 0 0 0 0 0 1 1 0 -- (R/W (1 bit) , write to 1 register only (2 bits) , address of register (5 bits)
Write cycle: 1 1 0 0 0 1 0 1
MSB BIT 7 CONTROL OUTPUT MODE SET TO 1 FOR TEST PATTERN
MSB BIT 6 CONTROL OUTPUT MODE SET TO 1 FOR TEST PATTERN
BIT 5 SET TO 0 NO INTERNAL TERMINATION ON LVDS
BIT 4 SET TO 0 NO INTERNAL TERMINATION ON LVDS
BIT 3 LVDS OUTPUT CURRENT 3.5mA
BIT 2 LVDS OUTPUT CURRENT 3.5mA
BIT 1 NORMAL OUTPUT MODE - MUST BE 0
IT 0 NORMAL OUTPUT MODE - CAN BE EITHER 0 OR 1 - I TRIED BOTH
Are the instruction and write cycle correct? Any suggestions would be appreciated.
Thank you,
-Marc