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help needed with test pattern out from ADS5400

Other Parts Discussed in Thread: ADS5400

I am writing through the 3 pin configuration of the serial interface to the ADS5400 from a Virtex 5 FPGA.  My question is to get a confirmation for  the proper bit sequence for the instruction and write cycle of MSB 7 down to 0. I cannot seem to get a test pattern out of the chip and it keeps defaulting to normal operating mode (LVDS is outputting sampled data bits). When I wrote to Register 5, I was able to verify back that I wrote correctly within a INSTRUCTION & READ cycles. Do I need to keep the serial communication low after the write cycle is complete for the test pattern out to work? 

The sequence I am sending for REGISTER 6 is:

Instruction cycle: 0 0 0 0 0 1 1 0 -- (R/W (1 bit) , write to 1 register only (2 bits) , address of register (5 bits)

Write cycle:  1 1 0 0 0 1 0 1 

MSB BIT 7 CONTROL OUTPUT MODE SET TO 1 FOR TEST PATTERN

MSB BIT 6 CONTROL OUTPUT MODE SET TO 1 FOR TEST PATTERN

BIT 5 SET TO 0 NO INTERNAL TERMINATION ON LVDS

BIT 4 SET TO 0 NO INTERNAL TERMINATION ON LVDS

BIT 3 LVDS OUTPUT CURRENT 3.5mA

BIT 2 LVDS OUTPUT CURRENT 3.5mA

BIT 1 NORMAL OUTPUT MODE - MUST BE 0

IT 0 NORMAL OUTPUT MODE - CAN BE EITHER 0 OR 1 - I TRIED BOTH

Are the instruction and write cycle correct? Any suggestions would be appreciated.

Thank you,

-Marc

  • Hi,

    Your description of how you write to the SPI port seems to be correct.  You do not need to keep the SPI enable (SDENB) low after the SPI write. 

    I have enable the modes for outputting the toggle and PRBS data before on the bench.

    Normally when I am debugging an interface to the SPI register space i like to test it with a write to a single bit that I can see right away if the desired thing is happening, like the powerdown bit.  I'll power the ADC EVM from a bench supply and then use the SPI port to set the power down bit and look to see that the current consumption dropped.  This way I know that I am writing to the correct address with the correct data.

    Some of the errors that can happen in the coding of the state machine in the FPGA to drive the SPI port in include getting the bit order reversed as to whether the bit 0 is sent first or last, and whether the SPI data is centered around the rising edge of the SPI clock or falling edge.  If there is an error in coding the format then reading back what is written is a good sign but still could be the wrong address. 

    Another common error is getting the pin assignment off so that the SPI signals are formatted right but to the wrong pins - you wouldn't have that issue if you can read back what you wrote.

    You may need to get out an oscilloscope to see that the SPI signals are doing what you expect them to do.   Try to write somethjing like 00000100 to address 00000010 and use the scope to make sure that the address comes out first before the data, and the address isn't flipped to be 00100000 or something like that.   Or that something is not inverted, and that the whole chunk of bits sent add up to 16.  (like if the FPGA code were trying to make the 5-bit address be a whole byte so that after adding the R/W bit and two bits for length the entier cycle becomes more that 16 bits - for example.  When coding up the SPI interface logic there can be lots of ways to mes sit up and scoping the signals at the ADC can make clear what happened sometimes.) 

    Regards,

    Richard P.

  • Thank you Richard P. for your most helpful post. I will follow your suggestions as I am sure that will clear up the problem.

    -Marc