Synchronize Capture of 2 x ADS42JB69EVM Boards

Thank you Jim.  I will check back in a couple of weeks.

Hi Jim,

Has the firmware been updated to support this?

Thanks,

Thai

Thai,

This firmware is scheduled to be released in about 2 weeks.

Regards,

Jim

Hi Jim,

Is an update available?

Thanks,

Thai

Hi Jim,

Is this problem still being worked on?

Thai

Jim,

I've installed version 3.0 of the HSDC Pro software but the trigger option isn't available, do I need to setup something?  Also, do you have documentation for setting up the 2xTSW14J56 boards for simultaneous capture?

Thai

Jim,

I looked into a few of the ini files but didn't find any with the "Is Capture Trigger SMA = 0" line.  Which ini file should I modify?

Thanks,

Thai

Thai,

I should have an answer for you about this by tomorrow.

Regards,

Jim

Hi Jim,

I also have questions regarding setup.

1)  The ADC EVM board has a reference out that is a square wave but we plan on providing the reference signal from another source to the reference in for both ADC EVMs.  Will a sine wave work or does it need to be a square wave.

2)  The user guide has setup for Software Trigger for the 1400 series board.  For our board, will the 4 SMA connectors provide the trigger or do we need an external trigger.

Thanks,

Thai

Hi Jim,

Do you have any update?

Thanks,

Thai

Thai,

I will try this myself today or tomorrow and let you know what I find out. I will also send your comments to the firmware design team.

Regards,

Jim

Thai,

If you enable software trigger then it will be in Master mode. If it is only in ext Trigger Mode then it will expect a trigger in slave mode.

You need to add the following line as shown below in the ADS42JB69_LMF_421.ini file:

Sysref Based Master Slave Trigger = 1

This file can be found at C:\Program files(86)\Texas Instruments\High Speed Data Converter Pro\14J56 Details\ADC files

[ADC]

Interface name="TSW14J56_MC_FIRMWARE"
Number of channels=2
Channel Pattern=1-1,1-5,1-2,1-6,1-3,1-7,1-4,1-8,2-1,2-5,2-2,2-6,2-3,2-7,2-4,2-8
\\Data Postprocessing=1:32768
\\operation:operand
\\operaion
\\0=bit shift
\\1=xor
\\2=and
\\3=or
\\4=not
\\operand
\\value(+ve if bitshift by right and -ve if bitshift by left)
\\E.g 0:-2,1:1024
\\bitshift by left 2 times and then xor by 1024
Number of Bits=16
Max sample Rate=250000000
Register_Config="-"
\\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
DLL Version=1.0
Device GUI Folder=ADS42JBxx EVM GUI
Read EVM Setup Procedure="EVM Setup Procedure not available"
\\use <> as delimiter for newline

[Version 1.0]

JESD IP Core_CS=0
JESD IP Core_F=1
JESD IP Core_HD=0
JESD IP Core_K=20
JESD IP Core_L=4
JESD IP Core_M=2
JESD IP Core_N=16
JESD IP Core_NTotal=16
JESD IP Core_S=1
JESD IP Core_SCR=0
JESD IP Core_Tailbits=0
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1
//extra parameter for megacore
JESD IP Core_JESDV=1

Sysref Based Master Slave Trigger = 1

MIF Config= 0.611G to 1.0G:RX:RX_PMA_x5,1.0G to 3.2G:RX:RX_PMA_x10
\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 0.611G to 1.0G:0x081010,1.0G to 3.2G:0x080808
Invert Sync Polarity = 1
\\Invert Sync polarity, 1:invert; 0: do not invert
Invert Serdes Data = 0 
\\Invert Serdes Data, 1:invert; 0: do not invert
Transceiver Mode = 0 
\\1:xcvr mode; 0: TX/RX only mode
Lane Mapping=lane0:0,lane1:1,lane2:2,lane3:3
\\Lane pattern for the LMF modes

Thai,

There is one more parameter that needs to be added to the ini file. This is called "Menu Enable="Trigger Option".  See below for where to add this.

[ADC]

Interface name="TSW14J56_MC_FIRMWARE"
Number of channels=2
Channel Pattern=1-1,1-3,1-2,1-4,2-1,2-3,2-2,2-4,1-5,1-7,1-6,1-8,2-5,2-7,2-6,2-8
\\Channel Pattern=1-1,2-1,1-3,2-3,1-5,2-5,1-7,2-7,1-2,2-2,1-4,2-4,1-6,2-6,1-8,2-8
Data Postprocessing=1:32768,0:1
\\operation:operand
\\operaion
\\0=bit shift
\\1=xor
\\2=and
\\3=or
\\4=not
\\operand
\\value(+ve if bitshift by right and -ve if bitshift by left)
\\E.g 0:-2,1:1024
\\bitshift by left 2 times and then xor by 1024
Number of Bits=15
Max sample Rate=1000000000
Register_Config="-"
\\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
DLL Version=1.0
Read EVM Setup Procedure="EVM Setup Procedure not available"
\\use <> as delimiter for newline
Menu Enable="Trigger Option"

[Version 1.0]

JESD IP Core_CS=0
JESD IP Core_F=2
JESD IP Core_HD=0
JESD IP Core_K=16
JESD IP Core_L=4
JESD IP Core_M=4
JESD IP Core_N=16
JESD IP Core_NTotal=16
JESD IP Core_S=1
JESD IP Core_SCR=1
JESD IP Core_Tailbits=0
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1
JESD IP Core_JESDV=1

Sysref Based Master Slave Trigger = 1

LED Debug = 1

MIF Config= 0.611G to 0.7G:RX:RX_PMA_x5,0.7G to 3.125G:RX:RX_PMA_x10,3.125G to 8G:RX:RX_PMA_x40
\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 0.611G to 0.7G:0x081010,0.7G to 3.125G:0x080808,3.125G to 8G:0x080202
Invert Sync Polarity = 0
\\Invert Sync polarity, 1:invert; 0: do not invert
Invert Serdes Data = 1 
\\Invert Serdes Data, 1:invert; 0: do not invert
Transceiver Mode = 1
\\1:xcvr mode; 0: TX/RX only mode
Lane Mapping=lane0:0,lane1:1,lane2:2,lane3:3
\\Lane pattern for the LMF modes
Group 128 bits Flag = 1
\\If 1, will group 128 bits from each DDR, and then apply the channel pattern
Is Capture Trigger SMA = 1
\\ 1- SMA J3 is Capture Trigger, 0 - BUSY_Z (G16 on FMC) is Capture Trigger
\\Skip JESD Config=1  

Connect a sma-to-sma cable between J3 of both boards.

The GUI will now enable the trigger function that is under the "data capture options" tab.

For the master board, enable the "Trigger mode enable" and "software trigger enable" options. For the slave board, enable only the "Trigger mode enable". Set up the slave TSW14J56 first. 

The master will send a trigger out on the SMA and also receive a trigger pulse internal to the FPGA when the user clicks on "generate trigger" on HSDC Pro GUI. The slave TSW14J56 should have the capture button replaced with "Read DDR Memory" and must be set first before issuing a trigger with the master. 

The trigger signal is referenced to the SYSREF signal to guarntee both boards will receive the trigger at the same time.

Regards,

Jim