I have a customer asking the following:
We are using two ADS42LB69 chips on a single circuit board and I am concerned about phase coherency between the parts. The tPDI value on page 10 of the datasheet seems to indicate that there is a 5 ns (13 ns - 8 ns) window of ambiguity on the input to output clock propagation delay. So if I have two chips on the same circuit board driven by the same 250 MHz (4 ns) input clock, that would imply that the output clocks are not necessarily phase coherent if one chip is operating at the min value (8 ns) and the other is operating at the max value (13 ns). They can be out of phase by more than a complete sample clock period. Is my interpretation correct? I am relatively confident that both chips will be operating at the same voltage and temperature, so how much of the ambiguity is due to process variation?
