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DAC5682Z Bypass FIR Interpolation

Kyle Yang
Prodigy 40 points

7762.FIR Porblems.docx

Hi, I am having a few DAC configuration problems.

Question 1:

Currently the CLK(external) is running at 125MHz, and the DataClk is running at 62.5MHz rate. As I sweep the input tone to the DAC close to 31.25MHz(125/4) from 0MHz, I am seeing an image tone ramping up around 31.25MHz on the spectrum analyzer. The CLK’s sampling image is presented around (125MHz – input tone freq), so I am wondering where the 31.25MHz image tone is coming from. (please see my configuration code below and pictures from the attachment). I believe that 2X interpolation is on.

Questions2:

According to datasheet,Table 1 Modes of Operation, we want to go with Mode 2X1. To do that, what is the correct configuration in terms of FIR and CMIX?

Also , from CONFIG2 - Address 0x2:
FIR2X4X: if not set, are FIR0 and CMIX0 being bypassed?? (FIGURE 32).

Scripts:

fpga_wr 1 0x1 0x10 ## FIR interpolation filters enabled

fpga_wr 1 0x2 0xc0 ## default register values, 2's complement input, dual DAC mode

fpga_wr 1 0x3 0x75 ## use SW_sync_bit, ignore external sync, B equals A

fpga_wr 1 0x3 0x78 ## set SW_sync bit, B equals A

fpga_wr 1 0x4 0x00 ## default register values

fpga_wr 1 0x5 0x42 ## reverse the LVDS input data, PLL disbled, DLL enabled

fpga_wr 1 0x6 0x0E ## PLL sleep

fpga_wr 1 0x7 0xFF ## default register values

fpga_wr 1 0x8 0x04 ## DLL restart

fpga_wr 1 0x8 0x00 ## clear DLL restart bit

fpga_wr 1 0x9 0x00 ## default register values

fpga_wr 1 0xA 0x00 ## default register values

fpga_wr 1 0xB 0x00 ## default register values

fpga_wr 1 0xC 0x00 ## default register values

fpga_wr 1 0xD 0x00 ## default register values

fpga_wr 1 0xE 0x00 ## default register values

fpga_wr 1 0xF 0x00 ## default register values

Scripts End

Please also see the attachment for pictures taken from the Spectrum Analyzer.

Thanks and Best Regards

  • 0
    TI__Genius 17290 points

    Hi Kyle,

    What you're seeing is expected. When interpolation is used the input signal bandwidth is limited to Fdata * 0.4. The problem is that the process of interpolation creates additional digital images at Fdata - Fin. It is up to the interpolation filter to remove the image, but the transition from the passband to stopband has a finite rollof. So the input frequency needs to be limited to Fdata * 0.4 to guarantee that the digital interpolation images sit in the stop band of the interpolation filter.

    If you sweep the signal around Fs/4 you should see the image following the response of the FIR0 filter showing in Figure 25 of the datasheet.

    So in your case, with Fdata = 62.5 Msps, the maximum input frequency should be limited to 62.5 MHz * 0.4 = 25 MHz. If you increase the signal above 25 MHz you'll start to see the interpolation image popup nearby. If you need to output a signal at 31.25 MHz you'll need to increase your data rate to 78.125 Msps.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Prodigy 40 points

    Hi Matt,

    Thank you for your guidance. I have some more questions related to the configuration from the first post:

    Current setup 1 (2X2 Mde):

    The dual Dac is on, Interpolation = 2. Applied the clock equation DataClk = DACClk * (# of Dac) / Interpolation,

    According to the equation above, my DACClk = 125MHz, so the DataClk is also 125MHz, and because of DDR fashion, my dataCLK into the chip from my FPGA is actually 62.5MHz. Then with Interpolation filter which operates on dataCLK, the input BW is limited at  62.5MHz*0.4 = 25MHz. Is my understanding correct?

    Current setup 2 (1X2Mode):

    Single DAC is on, Interpolation = 2, DACClk = 125MHz, so the DataClk is 62.5MHz, and because of DDR, my dataCLK into the chip from FPGA is actually 31.25MHz??, and the input BW limit is 31.25*0.4 = 12.5MHz??

    I cannot get this configuation(1x2) to work now because the dataCLK into the chip now is 62.5MHz. However, 1X1 Mode works, which I expected. Can you give me some insight into this ?

    Thanks and regards

    -Kyle