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ADC12J4000 to FPGA

Martin Siegele
Prodigy 50 points
Other Parts Discussed in Thread: ADC12J4000

Hi,

is there any reference design for any FPGA using the ADC12J4000 Evaluation Module? I just like to have something I can start with and don't want to spend 10k$ for a commercial A/D card. A reference design for the ADC12D1800RFRB would be fine too.

Thanks!

  • 0
    TI__Guru* 91947 points

    Martin,

    Which FPGA are you targeting? We have firmware for both Altera and Xilinx.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 50 points

    Hi Jim,

    I'm targeting Xilinx, which boards are suitable? I did not get completely how many JESD line the board would need and if TSW14J10EVM is needed.

    Thanks,

    Martin

  • 0 in reply to Martin Siegele
    TI__Guru* 91947 points

    Martin,

    TI sells a TSW14J10 that allows the user to interface an ADC12J4000 to a Xilinx KC705 or VC707 board. If you need to use 8 lanes (bypass mode) you will have to use a VC707 board as the KC705 only routed 4 lanes. The ADC can also interface to a TSW14J01, but TI never released this board. I do have some and maybe can spare one for you.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 50 points

    Jim,

    Thanks for the answer, but I don't get why I can't connect the ADC12J4000 directly to the Xilinx KC705 or VC707 board.

    Regards,

    Martin

  • 0 in reply to Martin Siegele
    TI__Guru* 91947 points

    Martin,

    You can connect the board directly. But if you want to use the TI software (High Speed Data Converter Pro), you will need this adapter board.

    Regards,

    Jim 

  • 0 in reply to jim s
    Prodigy 50 points

    Jim,

    do you have a reference design on which I can build up my design for Xilinx and if yes, where can I get it from? I would like to build a LIDAR for frequencies up to 500MHz. FFT and calculating the dominant frequency should be no problem, but it's not clear for me out of the datasheet how I get parallel data out of the 8 serial lines.

    Thanks,

    Martin

  • 0 in reply to Martin Siegele
    Prodigy 50 points

    Hi,

    I ordered now the ADC12J4000 and a Xilinx KC705 board. Is there any reference design I can use or do I have to start from scratch?

    Thanks,

    Martin

  • 0 in reply to Martin Siegele
    TI__Guru* 91947 points

    Martin,

    The KC705 only supports 4 lanes, so if you need 8 lanes, you will have to use another platform such as the VC707. Below is what Xilinx sent me to pass on to you. Please contact your local Xilinx rep for any questions regarding their firmware.

    The reference design can be downloaded directly from this page on the Xilinx website.

    http://www.xilinx.com/member/jesd204_eval/index.htm

    This page also gives you links to the documentation for the core so is the best starting point.

    Your best starting point would be to follow the documentation to generate the core with the configuration he requires then generate and update the GT for the correct line rate.You can then open and simulate the example design that is delivered in Vivado, this shows the core running!

    You will then only have to write a module that de-maps the samples.

    Regards,

    Jim