HI, all
Can the ADC08d1020 IO used to configure ADC be directly connect to 1.9V whitch is the supply of this ADC?
why in the evaluated board the I/O is connected to 1V8? Is that because the FPGA dosen't support 1.8V?
Thank you very much.
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HI, all
Can the ADC08d1020 IO used to configure ADC be directly connect to 1.9V whitch is the supply of this ADC?
why in the evaluated board the I/O is connected to 1V8? Is that because the FPGA dosen't support 1.8V?
Thank you very much.
Hello
In the ADC08D1020 and related product EVMs, the ADC power supplies are all at 1.9V. This includes the supply voltage for the LVCMOS I/O and the LVDS DATA, DCLK and OR outputs.
The FPGA I/O banks associated with the ADC LVCMOS inputs/outputs is operated at a 1.8V supply. This ensures that the logic outputs from the FPGA will not overdrive the ADC logic inputs.
The 1.9V LVCMOS logic outputs from the ADC will be slightly over-driving the 1.8V inputs on the FPGA I/O bank but this can be tolerated due to the low drive strength of the ADC LVCMOS outputs and the input voltage tolerance of the FPGA inputs.
Regards,
Jim B
Hi,Jim
Thank you very much.
According the reply,I am now planning to use 1.9v VA pull-up power for ADC LVCMOS IO which trace through a Level Translators(1.9V to 2.5V) to FPGA 2.5V IO bank. In this way, will save a power chip. Dose this will be ok?
Best Regards.
Hello
Your plan to use the level translator should work fine.
We would be happy to review your schematics of the ADC related circuitry before you build your boards. If that is OK with you, please attach a. pdf version of your schematics when they are ready.
Regards,
Jim B
Hi ZH
I will review the schematics and respond by end of day on Tuesday Sept. 16.
Regards,
Jim B
Hi,Jim
I am sorry to disturb you. I just need your valuable advice of the schematic.
Thank you.
Hi ZH, here is my feedback on the schematics.
Page 1 - ADC08D1020
Page 2 - Front End
Page 3 ADC PLL
Page 4 Power Supplies
I hope this is helpful.
Regards,
Jim B
Hi,jim.
Thank you for your busy schedule to review the schematic.Your advice is very helpfull.
Page 3 ADC PLL
Page 4 Power Supplies
I refer to the ADC0xD1520RB Reference Board that using LP3878 for LMX2541 supply.so I though it's ok then.
The source of VCC2V5 is TPS54620RHL whose input is 12V.
The EN inputs of power chips are compatible with the 5V level.
Because there is no ports in 3.3V bank of FPGA, I choose the TMP451 whose supply can be 2V5. what about using LM95235 which has one channel and upload the SMBCLK,SMBDAT to 2.5V while the supply is 3.3V.
Best Regards.
Hi ZH
That balun is a good choice for the clock path.
Regarding the voltage regulator for the LMX2541, that is fine. I made a mistake checking things too quickly yesterday and thought that was a switching regulator.
The TPS54620RHL will work fine as a pre-regulator for the ADC power.
I understand regarding the TMP451 choice. I think that should be OK, though we have not tried that specific device with the diode used in these ADC products.
Best regards,
Jim B
Thank you very much,Jim.
I will update the schemtic according to your advice.
Best Regards.