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1.9v or 1.8V for ADC08D1020 I/O

Other Parts Discussed in Thread: ADC08D1020, LMH6552, LMX2541, LM95221, TMP451, LP3878, LM95235

HI, all

Can  the ADC08d1020 IO used to configure ADC  be directly connect to 1.9V whitch is  the supply of this ADC?

why in the evaluated board the I/O is connected to 1V8? Is that because the FPGA dosen't support 1.8V?

Thank you very much.

 

  • Hello

    In the ADC08D1020 and related product EVMs, the ADC power supplies are all at 1.9V. This includes the supply voltage for the LVCMOS I/O and the LVDS DATA, DCLK and OR outputs.

    The FPGA I/O banks associated with the ADC LVCMOS inputs/outputs is operated at a 1.8V supply. This ensures that the logic outputs from the FPGA will not overdrive the ADC logic inputs.

    The 1.9V LVCMOS logic outputs from the ADC will be slightly over-driving the 1.8V inputs on the FPGA I/O bank but this can be tolerated due to the low drive strength of the ADC LVCMOS outputs and the input voltage tolerance of the FPGA inputs.

    Regards,

    Jim B

  • Hi,Jim

    Thank you very much.

    According the reply,I am now planning to use 1.9v VA pull-up power for ADC LVCMOS IO which trace through a Level Translators(1.9V to 2.5V) to FPGA 2.5V IO bank. In this way, will save a power chip. Dose this will be ok?

    Best Regards.

     

  • Hello

    Your plan to use the level translator should work fine.

    We would be happy to review your schematics of the ADC related circuitry before you build your boards. If that is OK with you, please attach a. pdf version of your schematics when they are ready.

    Regards,

    Jim B

  • Hi,Jim,I am deeply grateful  for your help.

  • 6406.adc08d1020_Sch.pdf

    Hi,JIm

    This is the ADC related ciruite of my schematic.

    Thank you.

  • Hi ZH

    I will review the schematics and respond by end of day on Tuesday Sept. 16.

    Regards,

    Jim B

  • Hi,Jim

    I am sorry to disturb you.  I  just need your valuable advice  of  the schematic.

    Thank you.

  • Hi ZH, here is my feedback on the schematics.

    Page 1 - ADC08D1020

    • I recommend DNP for R21 as the default. The higher output common mode setting for the LVDS outputs is not required for compatibility with LVDS receivers.
    • The backside pad of the device MUST be soldered to Ground. An array of vias should be used to connect the pad to the ground planes of the board for best grounding and proper thermal design.
    • I recommend adding an optional 0 Ohm resistive connection from ADC_VCMO to Ground in case AC coupled operating mode is ever required.

    Page 2 - Front End

    • With +5V and -5V supplies the LMH6552 HD2 performance will be compromised when operating at the ADC required common mode input voltage. See Figure 23 of the LMH6552 datasheet. To align the LMH6552 common mode requirements with the ADC it is recommended to skew the power supplies to +6.25V and -3.75V.
    • I have concern that the U5 level translation device will not automatically detect the signal direction because the loads do not meet the requirement of having higher than 50kohm pull-up or pull-down resistance. I recommend using a translator similar to the SN74AVC4T774PW which has selectable direction for each input/output pair.

    Page 3 ADC PLL

    • What is the planned clock frequency?
    • What is the part number of the T1 transformer? This device should be a 1:2 balun rated for good performance at the desired clock frequency.

    Page 4 Power Supplies

    • Please update the LMH6552 voltage regulators to provide +6.25V and -3.75V.
    • Please update the 3V3_PLL supply to a low noise regulator that conforms to the recommendations of the LMX2541 datasheet. The LMX2541EVM design can be used as a reference.
    • Where is the VCC2V5 source? Is this rated for the required current of the U30 and ADC?
    • Are all ENABLEx inputs compatible with the 5V level that will be on these enable signals?
    • I would recommend the LM95221 or related product over the TMP451 for ADC temperature monitoring. This device family has been proven in product EVMs.

    I hope this is helpful.

    Regards,

    Jim B

  • Hi,jim.

    Thank you for your busy schedule to review the schematic.Your advice is very helpfull.

    Page 3 ADC PLL

    • What is the planned clock frequency?   1GHz or 500MHz
    • What is the part number of the T1 transformer? This device should be a 1:2 balun rated for good performance at the desired clock frequency. The part number of  T1 is B0430J50100A00 which is the same as using in the ADC0xD1520RB Reference Board.

    Page 4 Power Supplies

    • Please update the 3V3_PLL supply to a low noise regulator that conforms to the recommendations of the LMX2541 datasheet. The LMX2541EVM design can be used as a reference.

                 I refer to the ADC0xD1520RB Reference Board that using LP3878 for LMX2541 supply.so I though it's ok then.

    • Where is the VCC2V5 source? Is this rated for the required current of the U30 and ADC?

                 The source of VCC2V5 is TPS54620RHL whose input is 12V.

    • Are all ENABLEx inputs compatible with the 5V level that will be on these enable signals?

                 The EN inputs of power chips are compatible with the 5V level.

    • I would recommend the LM95221 or related product over the TMP451 for ADC temperature monitoring. This device family has been proven in product EVMs.

                 Because there is no ports in 3.3V bank of FPGA, I choose the TMP451 whose supply can be 2V5. what about using LM95235 which has one channel and upload the SMBCLK,SMBDAT to 2.5V while the supply is 3.3V.

    Best Regards.

  • Hi ZH

    That balun is a good choice for the clock path.

    Regarding the voltage regulator for the LMX2541, that is fine. I made a mistake checking things too quickly yesterday and thought that was a switching regulator.

    The TPS54620RHL will work fine as a pre-regulator for the ADC power.

    I understand regarding the TMP451 choice. I think that should be OK, though we have not tried that specific device with the diode used in these ADC products.

    Best regards,

    Jim B

     

  • Thank you very much,Jim.

    I will update the schemtic according to your advice.

    Best Regards.