Hi,
I have just received the boards ADC12J4000EVM + TSW14J56EVM which I have purchased. We would like to do our own design based on this combination. In particular, we would like to connect an Arria V Altera FPGA to the ADC via the JESD204B interface. Would TI be able to send me the FPGA Verilog or VHDL design files that are used for the evaluation kit, in order to serve as a reference design?
Thanks,
Yair