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Interfacing ADS5404 with Xilinx

Other Parts Discussed in Thread: ADS5404

Hi, 

I've seen, that many high speed converters have been interfaced with Xilinx FPGAs. I want to interface ADS5404 converter. Is there a starting point or reference design available?

Thank you,

Christoph

  • Hi,

    All of our High Speed ADCs have been conencted to our capture cards such as TSW1400 or TSW1405 or the older TSW1200,  The TSW1200 used a Virtex4 while the TSW1400 uses Altera and the TSW1405 uses Lattice.

    We do provide the Verilog for the TSW1200 upon request, but the code would have to be adapted to the newer Xilinx devices.  (different delay settings for the IDELAY would be needed to close timing.)   We do not have specific reference designs for all our ADCs into all possible FPGAs.

    Attached is a sketch of how the ADS5404 would interface to a Xilinx.  The interface is very straightforward, once the optimal setting for the IDELAY tap setting is determined.  The static timing analyzer in the Xilinx design tools and appropriate timing constraints would be used to determine if the interface would close timing with a particular set of IDELAY settings.

    Regards,

    Richard P.

  • Hi Richard, 

    thanks for your comments. We have the TSW1400 and the ADS5404 in place (this works fine) and want to go with the extra adapter to a Xilinx KC705 Kintex eval Board in the first step. If that is possible, it would be great if you can send me some sample code for the TSW1200 as a support to start with the KC705.

    Thanks a lot,

    Christoph