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Verification of Schematics of ADS4249 custom board _ interfacing with Virtex-4 FX100

Ravi Teja Talluri
Prodigy 20 points
Other Parts Discussed in Thread: ADS4246

Hi,

I am Ravi Teja Talluri from Alpha Design Technologies Pvt LTD.,

I am looking for some assistance on our design.

Actually we are interfacing the ADC card to Virtex 4 - FX100 FPGA

we have following questions for the design

1) Where clock to ADC can be driven only through FPGA(BANK with 3.3volt Vcc) not through any other Clock Generator or Jitter Cleaner Circuitry?

2) ADC is configured to LVCMOS mode using SCLK,SEN and CTRL(0:2) and CLK_IN is differential?

-- we have observed on ADS4246 160MSPS device with LVCMOS CLK_IN configuration then CLK_OUT is not available.

In that case, what precautions have to be taken for the design.

I have also attached the schematics to this mail. 

Schematics_ADC_151014.pdf
  • 0
    TI__Genius 17290 points

    Hi Ravi,

    Not entirely sure what you're asking here, but I'll try to answer your questions as I interpret them.

    1. Yes, you can clock the ADC from an FPGA, however the noise performance will suffer because FPGA clocks have quite a bit of jitter. This will be most obvious when the input frequency is fairly high (> 100 MHz).

    2. It sounds like you're using the parallel configuration mode to set the part in CMOS interface mode. Make sure RESET is held high if you're using parallel configuration mode. For CMOS mode, you need to pull SEN to GND (per table 7 in datasheet). CLK_IN is still differential in CMOS mode, the interface mode will not effect the CLK input.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Prodigy 20 points

    Hi Matt,

    As discussed earlier in regards to ADS4246 @ 160MSPS custom Board.

    -- With 100 MHz sampling Clock the

    when both the Channels are terminated with 50ohm (No Input Signal case)

    output data of channel A is around +40 to +45 Counts with some sudden spikes to about +85 counts or +25 counts.

    where as output data of channel B is around -5 to -10 Counts with sudden spikes to about +7 counts or -14 counts.

    -- But When signal of 10 MHz is applied to both channels from a Signal Generator ...

    -- The amplitude change can be observed is only +10dBm to -60dBm.

    -- I have attached the screen shots for no input signal condition, please guide me as soon as possible.

    with termination.pdf