Hi,
I'm new to using the DAC3484 and I've seen the SLAA545 related document on the DAC3482. Just wondering if TI has a verilog or vhdl simulation model that I can download to simulate the recommended interface in SLAA545.
Also, the person who designed the hardware for our pcb has channels B and D of the DAC3484 tied to ground. It probably would have been better if they used the DAC3482 instead. Then, do I drive 0's during the clk phase that outputs chan B and D? Or is it okay to drive channel A data during the channel B phase and drive channel C data during the channel D phase?
Essentially, I'm driving the channel A data for two consecutive clks and driving channel B data for two consecutive clks. On a system or noise aspect would there be any problems if I drive channel A during the channel B phase even though channel B is grounded?
Thank you for your help,
Peter
