ADS42LB69 clock cycle requirement after clock started on

Dear Sir,

Please le me correct what I am asking.

I am referring to LTC2208 datasheet, It has TIME AFTER WAKE-UP OR CLOCK START (us).

Do you have similar data for  ADS42LB69?

Specifically I would like to know SNR after wake-up from shutdown or starting encode clock.  

Best regards,

Masa

Hi Eben,

I understand the latency- thank you. How about TIME AFTER WAKE-UP OR CLOCK START (us) will be?

Is it equivalent meaning to Wakeup time on page 7 in ADS42LB69 datasheet? Maximum Time to valid data after comming out of STANDBY mode is specified 100us.

So host system has to wait 100us(max) + ADC latency + tPDI(max) to get performance SNR specified in the datahset if ADC was STNDBY(controlled by Register x08-D5). 

Correct?

Best regards,

Masa

Hi Eben,

As a consideration, the standby mode will NOT be used. 

However I would like make sure the following points during normal operation mode;

Q1. Can Input clock be stopped without getting into standbymode?

Q2. What time will be required to get valid data after clock is restarted?

Q3. Even if input clock speed will be changed (not stopped) at normal operation, how soon the valid data can be ready at the output at new clocking speed?

All operation expected to run in normal mode (NOT standby mode).

Best regards,

Masa   

Hi Eben,

May I have your answer? Masa

Hi Eben,

Thank you very much for your answer. I understand.

Masa

Hi Eben
I would like to double check if the answer for Q2 (ADC Latency + tpDI) is correct for both AC and DC coupled CLKIN.


I met an issue below that is AC coupling.
e2e.ti.com/.../1691606

Best regards,
Masa

Masa.

The time the output clock is present after receiving a valid input clock is not measured so it is not specified in datasheet. But it will be better than wake up from global power down. The data is latency is pipeline’s latency plus combinational logic’s delay.

Regards,

Jim

Hello Jim

I asked another e2e slot

I understand data and clock output are different delay, but it does not make sense to have data valid without right clock output.

What is expectation of the delay?

Global power down wake up time is typ 200us and max 1ms . Is 20us (our measurement until valid CLKOUT)  delay expected as one between valid CLKIN and valid CLKOUT at just clock re-start (not power down nor standby mode)?

Best regards,

Masa

Masa,

The output clock will always be valid before output data is after power up or reset. It is just not measured.

Regards,

Jim

Jim,

I understand that it is not measured and no spec in datasheet.

What is your opinion if 20us delay from CLKIN to CLKOUT can be improved or expected? It is not rest nor power up but just re-start clock input.

Best regards,

Masa

Hello Jim,

Do you think if the 20us can be improved?

Best regards,

Masa

Masa,

It depends on context. For example, when device is powered up both output clock and data will develop towards valid output levels by same time since they are both generated from same serializer PLL. Wake up from global power down (which powers down the serializer PLL as well)  or interrupting input clock will also show output clock and data developing to valid logic levels by same time.

A snap shot in ADS41xx family (uses same DDR buffer, QDR will also follow this trend) is shown below:

 

Yellow curve is input clock, blue is output clock, green is output data. As you can note it takes some time for green curve to show stable data, however is reaches valid logic levels same time as blue curve (output clock).

 

If you put device in ‘output buffer disable’ mode, it selectively powers down the output ‘data’ buffers. In this case, output clock will still be available but output data will be tri-stated. Wake up from ‘output buffer disable’ is usually very fast – as soon as SPI write to enable output buffer gets effective (i.e. last active edge of SCLK, for example in 16bit SPI protocol last active edge will be 16^th SCLK edge), output buffer wakes up within no time(in few ns).

 

Regards,

 

Jim

 

ADS42LB49.pptxMasa,

The plot is attached.

Jim

Jim,

Thank you very much for your measurement and clarification of CLKIN and CLKOUT/DATAOUT.

I understand that CLKIN start recovery without standby mode nor power down will take PLL lock time around >15us not just ADC Latency + tpDI.

Best regards,

Masa