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ADS5474 DC Offset in Output Data

Other Parts Discussed in Thread: ADS5474, ADS5400

I notice that my ADS5474 output data has a DC offset about +5mV, which is about 37 codes above the zero output code. For a continuous sine wave input, the output data swings around output code 8229, not 8192 (zero code), 8229 - 8192 = 37. The sampling clock frequency is 400MHz. The sine wave analog input is 300MHz.

At the ADS5474 analog input pins, there are the AC coupling capacitors; therefore, the ADS5474 analog input should not have any DC offset.

Is this +5mV DC offset level normal or abnormal? If it is abnormal, what is wrong with the DS5474 circuit? How do I fix it to bring the DC offset to normal?

Tuan To

  • Hi,

    Actually, I see in the ADS5474 datasheet on page 3 that the offset error for the ADC is specified to be between the limits of -11mV and +11mV.   So seeing an offset of about 5mV would not be abnormal.   And this will vary from device to device within the datasheet limits.

    Your options would be to look for a device with tighter spec limits or to externally calibrate out the offset error.  For example, the ADS5400 has an internal register accessable through a SPI port that can be used to fine tune offset error.  Or the data could be post-processed to subtract off offset error in an FPGA.  One simple such algorithm could be to keep an average code or a pair of min/max values over a sliding window of time to calculate the actual offset and then use that to adjust each sample in real time.  The average would be done continuously to 'track' things like temperature drift or voltage drift, and would be of a long enough time constant to not be fooled by short-term pathological data patterns.  This is the kind of offset correction that might be done in cases where multiple ADCs in parallel are interleaved to effect a higher sample rate.  A fancier algorithm could be developed and tested as well.

    Regards,

    Richard P.