Hello All:
I meet a data acquired problem in 20-bit (serial output) ADC testing using TSW1400. The platform is like this: A CPLD is used to change 20-bit serial output to 7-bit parallel output and send a parallel output sampling clock, so the interface is looks like ADS4149 and the firmware of ADS4149 can be used. But I found a problem, If the 7-bit parallel output rate and the output sampling clock is higher than 3MHz, the TSW1400 can sample the data correctly; If the parallel output data rate and output sampling clock is at the vicinity of 2MHz, the TSW1400 would sample the data with some errorl if the rate is lower than 1MHz, the TSW1400 can not sample the data, and the USER_LED3 is off, which indicates that there is no valid clock. So I wonder know if it has a low-limit frequency of TSW1400?
And how can I solve the problem? if I increase the output sampling clock, it will decrease the valid memory depth. If I increase the speed of ADC, it will decrease the performance of ADC.
