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AFE7070 and TSW1400 set up for QAM

Eric Eckenrode
Intellectual 275 points
Other Parts Discussed in Thread: AFE7070EVM, AFE7070, CDC7005, CDCM7005

Hello,

We have a customer that has the AFE7070EVM hooked up to the TSW4100.   They set up the AFE7070 for dual output clock mode so they followed the reccomendations of 1.4.2 in the User's Guide (Couple of changes to resistors). 

http://www.ti.com/lit/ug/slou337/slou337.pdf

The eval system looks to be working correctly.   Bits are toggling at the output CMOS header into the AFE7070 board.  The AFE7070 is hooked pin 1 to 1 , 2 to 2 ,… and so on up to pin 34 of the AFE. Specs: 

1)   120 MHz Wenzel oscillator hooked to the LO input of the AFE.

2) J12 (ext clk) is connected to a 65 MHz signal generator set to 7 dBm.

3)  CLK IO sma is connected to cmos clk on the TSW using a short SMA. 

On the output there only seems to be a 120 MHz LO signal.  We are lookng for help on how to set up the GUI so that a QAM generator can be created.  On the  High speed Data Converter Pro v2.70 screen the correct(simulated) waveforms are displayed, and the send command seems to work.  The device is set to: CMOS_AFE7070.  The problem seems to be in the AFE software and control.  What other information should I supply?

Thanks,
Eric

 

 

  • 0
    TI__Genius 12965 points

    Eric,

    I will be able to respond to you in a day or so.  I'm currently looking for an EVM to set up the same configuration.

    Ken.

  • 0 in reply to Ken C
    TI__Genius 12965 points

    Eric,

    Its been a few days and I thought I would send you an update.  I have found an AFE7070 and TSW1400 and will work on confirming the clock modes.

    Ken.

  • 0 in reply to Ken C
    TI__Genius 12965 points

    Eric,

    I first verified that the AFE7070 EVM works with the TSW1400 using the default condition.  See attached pdf.  This should work as described.

    For dual output clock you have to move the R18 to R25 - this will set the CLOCK IO from the AFE7070 to drive the CLK IO J11 output.  Set the Clock Settings in the AFE7070 EVM GUI to Dual Clock.

    Move the CMOS clock SMA driving the TSW1400 from J5 CDC OUT to the J11 CLK IO sma connector.  This will enable the AFE7070 to drive the data clock to the TSW1400.

    Also you can 3-state all of the outputs of the CDC7005 except the DAC CLK (Y3A) output.  This ensures that the only clock from the CDCM7005 is going to the AFE7070.  The data clock CLK IO now has to come from the AFE7070.

    This worked fine and I get the expected output at the RF output J3 SMA.

    5460.AFE707xEVM_Quick_Guide_TSW1400.pdf

    1541.AFE7070 Dual clock settings.pdf

    Ken