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ADC12J2700 JESD setting

David Park
Expert 5440 points
Other Parts Discussed in Thread: ADC12J2700

 

Hi,

Customer is considering FPGA with 1000 of I/0 and 24 of Serdes.

But they want to adopt several ADC12J2700 per 1 FPGA so they can use 5-lane per 1 ADC12J2700 for JESD link.

1. Can 5-lane of JESD204B use for 1 ADC12J2700?

2. if decimation is used, sample will be decrease. With keep sample number, can customer use 5-lane of JESD204B?

Thanks in advance

  • 0
    TI__Mastermind 43930 points

    Hi David

    1) With 5 lanes per device, the lowest decimation factor available is Decimate by 4.

    2) With decimation off (DDC Bypass Mode) there will always be 8 active output data lanes. There is no reduced lane count mode when decimation is off.

    Best regards,

    Jim B