ADS4145 - Will inputs support 2.5V CMOS levels?

Matt,

Thanks for the quick response!

John

Follow up question to this regarding the ADS4126 (a similar device). When driving SCLK, SDATA, and SEN at voltages higher than 1.8V, will there be increased current due to a clamping circuit?

What's the spec for the current draw when operating at 2.5V or 3.3V?

Don

Thanks Jim,

Appreciate the timely response.

Don

Don,

In ADS4145, SCLK, SDATA and SEN pins are allowed to be driven with 3.3V logic levels.

SCLK and SDATA have 180K Ohms to ground, and SEN has 180K Ohms to 1.8V AVDD supply which forms a weak pullup..

ESD diode from pin to 1.8V supply is removed so that 3.3V logic level can be supported.

ESD diode from ground to pin is present in all these pins.

Regards,

Jim

Thanks Jim,

A few additional questions.

1. With no top-side ESD structure, is ESD managed via the bottom structure only?

2. The design in question is a board that will be hot-swapped.   Should we be adding external high-side ESD structures to guard against traces being exposed to human hands?

Thanks.

Don

Don,

I am checking with the designers regarding this.

Regards,

Jim

Don,

The answers are "Yes" and "Yes, if possible".

Regards,

Jim

Thanks Jim,

We're a little short on PCB space.   What would happen if we don't put external ESD structures on the high-side?    How does that degrade ESD robustness on these pins?

Don

Don,

I have passed this along to the design team. Hope to have an answer soon.

Jim

Don,

If space permits, place an ESD diode from the pin to 2.5V.

If you do this, since these are digital input pins, this should work as long as valid logic levels are being crossed with sufficient timing (setup/hold) on these pins.

Regards,

Jim

Thanks Jim,

Appreciate the speedy response.   But I'm not sure you answered my original question.    That is:

What would happen if we don't put external ESD structures on the high-side?    How does that degrade ESD robustness on these pins?

We can bury the SPI lines so that no-one could touch them, but then we'd be relying on the internal weak and poorly defined pull-up resistors in the FPGA to set the standby mode at startup.   We've see the ADS4126 go into standby in this configuration, but it's marginal.    We could address this by resetting the registers at startup, but it's not defined too well in the datasheet.   

If we need an external ESD structure, then so be it.   We have two possible courses of action then:

1. We'll include an external ESD structure and external strong(er) pull-up resistors to guarantee startup behaviour.  If you have an ESD part recommendation, that would be ideal.   

2. We'll bury the traces.   If we do this, we need to know the following:   If after power-up, we apply SDATA = 0V, and issue a reset pulse (>10ns), the SPI bus of the device is guaranteed to be alive.

Thanks again for the speedy responses.  

Don

Don,

For #1, I do not have an ESD part recommendation.

For #2, there is no requirement for the level of SDATA during reset. There is a requirement for SEN to be high during the reset pulse though (Figure 6 of data sheet).

What do they mean by "We will bury the traces?".

Regards,

Jim 

Don,

The decision of keeping the ESD diode to 2.5V purely depends on what these pins are expected to see.

If the voltage surges on these pins (may be from driver) are frequent, you may want to keep diode structure.  Though I don’t have a specific recommendations, you might look at clamping diodes such as MMBD352.

 

Regarding SPI mode; the function is hard-wired.   When RESET pin is held HIGH, device enters in parallel mode. When RESET pin is pulled down to LOW logic, device enters in SPI mode.

Regards,

Jim