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ADC16DX370 and DAC38J84 Latency

Jonathan Valdez
Genius 16430 points
Other Parts Discussed in Thread: DAC38J84, ADC16DX370

Hello,

Should be an easy question

Background:

I am working with the ADC16DX370 and DAC38J84. Looking through the datasheets, I see only a typical latency measurement.

Questions:

1) What is the worst case propagation delay from input to output for the ADC16DX370?

2) What is the worst case propagation delay from input to output for the DAC38J84?

  • 0
    TI__Genius 17290 points

    Hi Jonathan,

    The DAC38J84 latency is heavily dependent on the configuration. The worst case estimate is over 1000 DACCLK cycles in 16x interpolation mode. The best case estimate is closer to 250 DACCLK cycles.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    TI__Genius 17290 points

    Jonathan,

    For the ADC16DX370, the worst case delay is around 19.5 frame clock cycles. This is the summation of tLAT_ADC and tD-DATA as shown in figure 6. Note that the FPGA receiver will add quite a bit of additional latency. The frame clock is equal to the sampling clock for this device.

    Regards,
    Matt Guibord