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DAC5682 self test mode - no output

Other Parts Discussed in Thread: DAC5682Z

We configure a DAC5682 in self test mode following these
1) CLKIN/CLKINC it is stable 62MHz with common mode voltage at 0.9V which is CLKVDD/2
2) RESETB toggles low for 2ms.
3) Registers programmed and the read back values are:
Reg: 0x0 Value:0x3
Reg: 0x1 Value:0x18
Reg: 0x2 Value:0xea
Reg: 0x3 Value:0xb0
Reg: 0x4 Value:0x0
Reg: 0x5 Value:0x6
Reg: 0x6 Value:0xf
Reg: 0x7 Value:0xff
Reg: 0x8 Value:0x0
Reg: 0x9 Value:0x0
Reg: 0xa Value:0x0
Reg: 0xb Value:0x0
Reg: 0xc Value:0xa
Reg: 0xd Value:0x55
Reg: 0xe Value:0xa
Reg: 0xf Value:0xaa
4) SYNCP/N is set to high

On the output we see a constant voltage around 3V (no ramp voltage like a self test should produce).

What could be the issue? We run out of ideas and really need help with this.

Thanks,

Valentin

  • We disconnected the IOUTA1, IOUTA2 from everything and connected those two outputs to two 18ohm resistors which have the other end connected to AVDD (3.3V). The output on any IOUTA1, IOUTA2 doesn't look like a voltage ramp but we do see some values changing there every 16ns (period of CLKIN) - see the picture bellow.

    For self test do we need to have DCLKP/N or not? The data sheet mention only to have CLKINP/N stable for self test. 

  • I don't see the picture I inserted before so I tried again - hopefully it does work.

  • Valentin,

    The Digital Self Test in the DAC5682z is not a ramp signal, but rather a digital pattern based on an LFSR (pseudo-random). You should see max and min signal toggling at the analog output at the CLK rate with various amplitudes.

    It looks like you followed the Digital Self Test Mode in the data sheet of the DAC5682z (~page 42), you should get the toggling analog output as you see.

    Ken

  • Ken,
    Thanks for clarifications - somehow I got the impression the output is a ramp in selftest mode.
    Now, your proposal from a previous thread to test by setting the DAC in offset binary and turn on CM1 to Fs/4 makes sense - this is the way to do it to get a well known signal on the output.
    We have some issue on the LVDS data lines going to the DAC so my question is - if we set the dac sync line to 0 will the data send to the DAC be zero in that case so we could see the full scale tone on DAC output?
    We found this in the datasheet: "If SYNCP is low, the transmit chain is disabled so input data from the FIFO is ignored while zeros are inserted into the data path" so if I understand this correctly if SYNCP is low the data inserted in the DAC is zeros.
    Here SYNCP low means the SYNCP line out of the pair SYNCP/N to be connected to ground? or is actually the SYNC differential signal to be 0 logic?
    Valentin
  • Valetin,

    The SYNCP reference should be SYNCP/N - you need a logical 0. It should work as stated to give you all 0s for fullscale negative in offset binary mode.

    If this is problematic please look into Config 3 register to use SW_Sync option to replace the LVDS signal with the register setting instead.

    Ken.
  • Ken,
    I use the SW_Sync option but all I get at DAC output is a constant voltage around 3.12V (both outputs are connected to two 18ohm resistors connected to AVDD which is 3.3V).
    My DAC registers are:
    Reg: 0x0 Value:0x3
    Reg: 0x1 Value:0x10
    Reg: 0x2 Value:0x48
    Reg: 0x3 Value:0x71
    Reg: 0x4 Value:0x0
    Reg: 0x5 Value:0x0
    Reg: 0x6 Value:0xc
    Reg: 0x7 Value:0xff
    Reg: 0x8 Value:0x0
    Reg: 0x9 Value:0x0
    Reg: 0xa Value:0x0
    Reg: 0xb Value:0x0
    Reg: 0xc Value:0x0
    Reg: 0xd Value:0x0
    Reg: 0xe Value:0x0
    Reg: 0xf Value:0x0
    What could be the issue?
    Valentin
  • On my previous experiment DCLKP/N, SYNCP/N and DATAP/N lines were all disabled in the FPGA

    If I enable DCLKP/N, SYNCP/N in the FPGA (CLKIN/C is always enabled and is 62MHz) and I use the registers values from my previous post I get this on my scope:

    So, there is still something not set properly.

    Do you know for sure that using CM1 and offset binary together with SW_sync _sel will work?

  • Valentin,

    Let me check something on the EVM and get back with you. Your register settings look correct.

    Ken.
  • Valentin,

    I just checked and the SYNCP/N signal low will send a 0 amplitude signal into the system, not all binary 0. As such the output is disabled completely (0 amplitude signal) if SYNCP/N is set low (either on HW pin or via register bit). In essence the SYNCP/N also acts as a TXENABLE function.

    The only way to use the CM1 and offset binary mode is to set the input LVDS pins to all logic 0 or all logic 1. You had mentioned you have some issues with your digital interface - are you able to set the digital interface to all 0 or all 1? Or at least the MSB? You can then use this and ensure SYNCP/N (pin or register) is high so that you do get an output. I tried your above register set on a DAC EVM with reg 0x3=0x73 (SW_SYNC enabled) and I get the expected output.

    Ken.
  • Ken,
    The issue we have with the LVDS bus is that the common mode voltage of the LVDS data lines is not 1.2V like it should but around 0.8V which is bellow 1V specified by the DAC. If I set only the MSB and SYNC, will that generate an output even though the other data lines are not driven by FPGA?
    Valentin
  • Ken,

    So we were able to set the 5 MSBs of the DAC to 0 and the common mode voltage will go down only to ~1V.

    We do get this output from the DAC:

    Is this the expected output? If we don't drive the dac DATA0-DATA10 from FPGA what is the value of these line in the DAC? Do they have some pull-up in the DAC?

    Getting this output is very useful for us as we could move on with testing the analog front end.

    Valentin

  • For LVDS there are no default pull up or down. The digital levels may be random unless the voltage is pulled above or below the common mode voltage for the LVDS.

    For a DC level into the mixer, the output is outlined in Table 7 and Table 8 for the CMixer blocks. For the same DC level in A and B channels this looks correct.

    Ken.
  • If the LVDS are not driven properly they will randomly go to some digital level. The lines that can be driven properly will latch properly. You will still get some output if just the MSB are driven properly.
  • Yes - I think I answered this in your other thread.

  • Valetin,
    I believe I answered this in another of your threads.
    Ken.