Hello,
I am currently checking the interfacing of the ADS5401 generating test patterns according to what the manual says. I have a couple of questions about that:
1) According to the manual and to what I tried I can generate two test pattern values and toggle between them. Is there a way of generating for instance a ramp signal with the test pattern to test the interfacing with the full 12-bit configuration ?
2) I can't find a lot of information about the test pattern ability of the ADS5401. For instance and since there are two interleaved ADCs, are the test pattern generating this way:
reg 0x3C => test pattern generated by the Even ADC (operating on the positive edge of the clock ?)
reg 0x3E => test pattern generated by the Odd ADC (operating on the negative edge of the clock ?)
reg 0x3D => test pattern generated by the Even ADC (operating on the positive edge of the clock ?)
3) I observe that when generating and toggling AAA and 555 and playing with the interfacing between the ADS5401 and the FPGA, half of my read-out samples has worse performances. It does not depend on the generated test pattern but I guess on which interleaved ADC is used. Can it be due to the fact that one interleaved ADC operate on the positive edge of the clock and the other one on the negative edge ? Can we expect an asymmetry ?
Thanks a lot in advance,
Antoine.