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ADS5401 test patterns

Other Parts Discussed in Thread: ADS5401, ADS5402

Hello,


I am currently checking the interfacing of the ADS5401 generating test patterns according to what the manual says. I have a couple of questions about that:

1) According to the manual and to what I tried I can generate two test pattern values and toggle between them. Is there a way of generating for instance a ramp signal with the test pattern to test the interfacing with the full 12-bit configuration ?


2) I can't find a lot of information about the test pattern ability of the ADS5401. For instance and since there are two interleaved ADCs, are the test pattern generating this way:

reg 0x3C => test pattern generated by the Even ADC (operating on the positive edge of the clock ?)

reg 0x3E => test pattern generated by the Odd ADC (operating on the negative edge of the clock ?)

reg 0x3D => test pattern generated by the Even ADC (operating on the positive edge of the clock ?)

3) I observe that when generating and toggling AAA and 555 and playing with the interfacing between the ADS5401 and the FPGA, half of my read-out samples has worse performances. It does not depend on the generated test pattern but I guess on which interleaved ADC is used. Can it be due to the fact that one interleaved ADC operate on the positive edge of the clock and the other one on the negative edge ? Can we expect an asymmetry ?

Thanks a lot in advance,

Antoine.

  • Antoine:
    We will be investigating these questions and will be able to respond thoroughly after the Winter Break. --RJH
  • Hi,

    1)  There is not the option for having the device generate an arithmetic counting pattern (ramp pattern) like we do in some other ADCs.  The ramp pattern is a very useful pattern for FPGA interface debug and so our newer devices often include this.  But the ADS5401 does not offer this pattern.

    2) The datasheet describes the test pattern generation for a two channel device such as ADS5402, but should be made more clear and should also be edited further for the single channel device so as to avoid confusion.  The way registers 3C, 3D, 3E work is that channel A will alternate between the contents of register 3C and 3D.  Channel B will alternate between the contents of register 3D and 3E.    Since the ADS5401 is a single channel device there is no need to mention register 3E in this data sheet.  If you program the same data pattern in 3C and 3E then the device will output that constant pattern.  If you program 3C and 3D with something different then you can make the output data toggle, such as if you put pattern AAA in register 3C and 555 in register 3D.

    3)  I would not expect an asymmetry between the output of the two patterns.  The output timing should meet datasheet specifications regardless of the AAA or 555.

    Regards,

    Richard P.