This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Thai,
Can you send me the ini file? By default, SYSREF is not currently used by the ADC on this evm and this may be the problem. Since the GUI does a new synchronization everytime a capture is issued, the time for synchronization to occur will vary. I will get more information for you regarding this setup.
Regards,
Jim
Hi Thai
The default configuration files for the ADC12J4000EVM has the SYSREF clock to the ADC turned off. I can send you some register configuration files that will enable SYSREF output from the LMK04828 and SYSREF processing in the ADC.
The files I will send are specific to the DDC mode, clock source and sample rate.
Given the earlier information you sent I assume you are using the raw 12 bit DDC bypass mode of operation. Please let me know if this is incorrect.
Can you confirm what sample rate (DEVCLK frequency) you are using?
Are you using the onboard clock source, or external clocking?
Best regards,
Jim B
Hi,
I am also having problems with trigger performance using external trigger source on TSW14J56EVM with ADC12J4000EVM. It seems that on some of the captures that I take start time of acquisition has a large offset. I am not trying to make a simulataneous capture on two master-slave boards, just a capture on single board on external trigger. Is this also related to the SYSREF configuration? Thank you for any insights.
Also, is there any specification on jiter in trigger activation time?
Hi Jurgis
Sorry for the delay getting back to your latest post.
How much time do you define as a large offset from trigger application to capture of the ADC data?
The trigger based system is mainly intended to allow synchronizing multiple boards, and to give outside control over data capture. It is not optimized for low latency response to trigger.
Best regards,
Jim B
Hi Jurgis and Bing
The TSW14J56 firmware receives the trigger input, and then waits until the next Start of Multi-Frame before initiating the storage of data. Given the firmware architecture we use in the TSW14J56EVM it isn't possible to start buffering data at arbitrary times, it must begin at Start of Multi-Frame.
If the Trigger pulse is asynchronous to the JESD204B Multi-frame, there will be variable delays. The variation will be a maximum of K frame periods for the ADC mode in use, where K is the number of Frames per Multi-Frame. The frame period in time can be calculated as:
T_Frame = (F * 10) / Fbit where F is the number of Octets per Frame, and Fbit is the bit rate of the JESD204B data interface. After 8b10b encoding there are 10 bit-times per octet, so there are F * 10 bit-times per frame.
I hope this is helpful.
Best regards,
Jim B