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DAC3484 FIFO erros - sync'ing

Other Parts Discussed in Thread: LMK04828

Hi,

In page 72 of datasheet it says that for single source it is recommended that a single pulse is used. I verified the timing of the interface with IOTEST and frame/sync are ok there with no errors. We scoped the signals are they look withing the margins.

After sync'ing the FIFO (use SIFsync or FRAME), clear the alarm (0x5)) and readback the alarm, we get :

 alarms_from_fifo = 111 which indicate a fifo collision. I attempt to resync and get the same error.

Usually for FIFO this would happen when clocks are not correct. I am sending a 122.88MHz DATACLK, with a 491.52DACCLK and interp by 8 setting.

DATACLK comes from an FPGA that gets the 122.88MHz clock from the same LMK as the 491.52MHz clock that is sent.

We are following the sequence for startup and resync as in pg 72..

Could you advise on next steps? I scoped the clocks in the board and they look clean, DACCLKGONE and DATACLKGONE are not asserted in the DAC thus saying those are correctly received.