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ADC12J4000EVM input signal

somad biaraa
Prodigy 60 points
Other Parts Discussed in Thread: ADC12J4000EVM, LMK04828

Hi,

We used vc707 xilinx board to capture adc12j4000evm 's data. it works correctly when input signal is in -50 to -20 dbm , but unfortunately  the received data is not True for input power beyond -20 dbm.

Adc  sampling frequency is 3760 MHz and works in bypass mode

As well , ramp test mode & short transport test mode &  adc test pattern passed successfully.

Where is the problem?

Thanks

Somad

  • 0
    TI__Mastermind 43930 points

    Hi Somad

    Can you send exported data files (text format with 12 bit values in a single column, at least 2k samples) for the following cases:

    1) ADC test pattern mode

    2) <-20dBm input

    3)  >20dBm input 

    Are you using vc707 code provided by TI or is it your own design?

    Thanks,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 60 points

    Hi Jim

    The exported data files are provided below:

    1-ADC test pattern data: 12 bit binary 1024 data (name:data_out) & it's index(name:counter_out)

    ADC_test_pattern_waveform.rar

    2- <-20dbm data: 12 bit binary, signed, 1024 data (name:data_out) & it's index(name:counter_out)

    under_20_waveform.rar

    3->-20dbm data: 12 bit binary, signed, 1024 data (name:data_out) & it's index(name:counter_out)

    beyond_20_waveform.rar

    I used my own design to capture data from adc12j4000evm.

    Is there any provided design by ti for vc707? can you send it for me?

    Thanks,

    Somad

  • 0 in reply to somad biaraa
    TI__Mastermind 43930 points

    Hi Somad

    Can you confirm the setting you are using for the SFORMAT bit? It looks like you have this set to 1 and are planning to use Signed 2's complement mode. Is that correct?

    Can you repeat the capture experiments with <-20dBm and >-20dBm signals with SFORMAT set to 0 and send that data as well? Please use an input frequency around 300-400 MHz if possible. Lower frequencies should make it a little easier to look at the expected sinewave signal.

    We do have a solution which supports the ADC12J4000EVM with the VC707. It utilizes the TSW14J10EVM available here (http://www.ti.com/tool/tsw14j10evm) to configure the VC707 and provide a command/data interface between our High Speed Data Converter Pro GUI and the VC707.

    The Xilinx firmware source is available from a link on the TSW14J10 folder: http://www.ti.com/lit/zip/slac690 If you need additional support with the source please work with your Xilinx support team directly.

    The latest High Speed Data Converter Pro software (http://www.ti.com/tool/dataconverterpro-sw) installation has most of the required files including the compiled Xilinx firmware.

    To configure the LMK04828 clocking devices on the ADC12J4000EVM with proper FPGA clock frequencies, one of the attached two files will need to be loaded using the Load Config button on the Low Level View tab of the ADC12J4000EVM GUI. One file (LMK04828_DB1_Fs_3100Msps.cfg) should be used for ADC sample clock frequencies up to 3100 MHz, the other file (LMK04828_DB1_Fs_3500Msps.cfg) will support operation above 3100 MHz.LMK04828_DB1_Fs_3100Msps.cfgLMK04828_DB1_Fs_3500Msps.cfg

    Best regards,

    Jim B