FPGA design on ADC08D1520RB Virtex-4:
1. ADC08D1520RB board cannot be detected by Xilinx IMPACT
After debugging, the original design pass Implement Design and generate .bit file ready. However, impact returns that it cannot find cable. All Xilinx solutions I found are to uninstall/reintall usb driver or install a winusb drive coming with ISE installation package. I tried all of them but the issue remains, although I can see the device is recognized in Device Manager in windows 7. I run out of solutions. :(
2. I design new control logic and signal processing algorithm in FPGA. My design did not introduce new input or output, or any DCM change. However, during Implement Design Xilinx ISE fails Place&Route. In Design Summary, I am told that my design consumes 101% of IOB and 150% DCM_ADVs. How could this happen?
3. I change my signal processing algorithm which has less memory occupation. Interestingly, then my design pass Place&Route, although Design Summary returns the same consumption of IOB and DCM_ADVs. Why? How does memory consumption matter to IOB and DCM?
4. What is the exact all returns of WvBoardReadCaptureData? The DLL document does not give a clear description on it. Based on wvdll.h as following, I am unable to find the answer. I saw 3 returns in examples by using the function. What want to confirm what are they exactly.
WvBool Wv_API WvBoardReadCaptureData(
WvWord board_index,
WvWord dut_index,
WvWord* return_data,
WvWord sizeof_data_allocated_by_caller,
WvBool* return_data_valid
);
Thanks.
-Bridget
