ADC16DV160 - DC Offset Issue on Captured Data

Hi John,

The capacitors at the input are not likely to cause a DC offset issue. Note that the ADC inherently has some DC offset. Large DC offset issue may be due to one of the following:

- DC coupling to the ADC input and components further up the signal chain creating a DC offset

- Incorrect data capture - somehow the output data bits are not being correctly put back into 16-bit samples, creating an offset. Can also be caused by the analysis script assuming a sample resolution different than 16-bits.

- Trying to drive the ADC analog input single-ended. This is not recommended.

Regars, Josh

Hi John

How will I come to know whether incorrect data capture is happening?

Hi John

I doubt I am not doing the data caoture correctly. Moreover, my captured data is clean hen i see 4K samples, but very bad when i see 32k samples from 1hz to 78mhz.

Moreover, I can see a dc offset of 2.3V at the input of the anti aliasing filter before the ADC and an offset of 1.13V at the output of this filter and the input of ADC. Will this offset create problems? If yes, how can I remove them?

Hi Sarika
Can you send txt files containing the 4k and 32k samples you are referring to?
When creating your reply click on the 'Use rich formatting' link below the right edge of the response window. That will bring up additional options for formatting and allow attaching files.
If you could attach the schematics for the signal path circuitry up to the ADC and the ADC connections that would also be helpful.
Best regards,
Jim B

Hi John

That problem is now coming with both 4k and 32k samples. We are getting a lot of spikes in the captured data. Moreover the noise floor looks high.

Hi Sarika

To confirm the issue is not caused by problems with data capture, please enable the Fixed Pattern data mode.

Set Register 00h Bits 6:5 to 11. (Fixed pattern mode instead of Normal Operation)

Then adjust the register settings at Registers 08h to 0Bh to generate patterns that will be useful for capture. I would recommend the following.

08h = 04h (pattern 000, then 001)

09h = 4Ch (pattern 010, then 011)

0Ah =  94h (pattern 100, then 101)

0Bh =  80h (pattern 100, then 000)

This will give a repeating sequence of data as follows:

• 0000 0000 0000 0000
• 1111 1111 1111 1111
• 1010 1010 1010 1010
• 1000 0000 0000 0000
• 1111 1111 0000 0000
• 0000 0000 1111 1111
• 1111 1111 0000 0000
• 0000 0000 0000 0000

If the problem is related to data capture, the first thing to try would be shifting the Output Clock Phase adjustment. Register 01h, Bits 4:2 allow the output data clock to be adjusted earlier and later than the default position.

If pattern mode capture works OK then the issue is not data capture and must be caused by some other problem (configuration, clocking, input signal path etc.)

Best regards,

Jim B

 

Hi Jim

I did pattern test with the fixed atterns suggested by you, with with the default phase of 95dg.
The output in hex as per my understanding should be:
0000
FFFF
AAAA
8000
FF00
00FF
FF00
0000

The output I am getting is :

0000
FF00
FFFF
0000
8000
AAAA
00FF
FF00
0000

What can be the problem?

Hi Sarika

I think you are almost getting the correct data but for some reason are getting pairs of samples out of order before the final result.

Here is a comparison between the correct pattern, what you are seeing, and what is possible by swapping every pair of samples:

Expected Pattern	Reported Pattern	Reordering data pairs
0000	0000
FFFF	FF00
AAAA	FFFF	0000
8000	0000	FFFF
FF00	8000	AAAA
00FF	AAAA	8000
FF00	00FF	FF00
0000	FF00	00FF
0000	0000	FF00
FFFF	FF00	0000
AAAA	FFFF
8000	0000
FF00	8000
00FF	AAAA
FF00	00FF
0000	FF00
0000	0000
FFFF	FF00
AAAA	FFFF
8000	0000
FF00	8000
00FF	AAAA
FF00	00FF
0000	FF00

Please check your capture firmware to see if there is any way that pairs of samples could be out of order.

Best regards,

Jim B

Hi Jim

I think what I am getting should be the result of the pattern test. Please check once.

But I am getting this till 2k sample depth. Once I increase the sample depth to 4k or 8k the number of error bits increases with increasing sample depth?

Hi Sarika

There is nothing in the ADC structure or output timing that will result in different results between the first 2k and later samples.

I recommend reviewing your data capture and storage design to identify the cause of the error bits when the sample depth is increased.

Best regards,

Jim B