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How to properly clock ADS4249EVM from FPGA

Ivan Bayan
Prodigy 10 points
Other Parts Discussed in Thread: ADS4249EVM

Hi.

I have ADS4249EVM and DE0-NANO board the question is how i can clock it from FPGA. FPGA have 3.3V output, in documentation for ADS4249EVM i found that it need 1.1Vpp for clock signal. For first time i made resistive divider, it work ok up to 20MHz
I looked for level translators and want try  to shift 3.3V to 1.2V for example. I feel that it's a common question and there is must be simple solution.
Is any idea?

PS
Yeah i know that resistive divider is a worst solution and  that clock ADC from FPGA not a good idea too.

  • 0
    TI__Genius 17290 points
    Hi Ivan,

    A couple issues here. FPGA CMOS outputs typically have limited current sourcing capabilities (10 mA or so). The default EVM clock input will load the FPGA output with a 50 Ω load, which is probably too much for the FPGA outputs. A better choice would be a 1.8V CMOS output, if available. If 3.3V is the only option, you could consider putting in some RF attenuators in the path to knock the signal down. My guess is that the 3.3V will be overdriven and the FPGA current limit will limit the swing to about 1 Vpp which will arrive at the ADC clock input as 2 Vpp differential (from 1:4 impedance ratio transformer) which would be acceptable.

    Secondly, there is no AC coupling on the EVM clock input, so you would need to put in a DC blocking capacitor before the EVM if there isn't one on the FPGA board. The transformer (T6) will ground the CMOS output without a DC blocking capacitor.

    On an actual board implementation (not using the EVMs) you could tie the FPGA CMOS output directly to the clock input without termination. This would work fine for a 20 MHz clock. See figure 53 in the datasheet for a diagram. If the routing is long or signal integrity is a concern, the better approach may be to use an LVDS clock with 100-Ω termination.

    Regards,
    Matt Guibord