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ADS 5400 Over Range, Reset and Output Clock Synchronization

Jeng Lee
Prodigy 20 points
Other Parts Discussed in Thread: ADS5400

ADS 5400 datasheet describes the behavior as Over Range (OVRA) flag occurs, which can indicate either below or above the full range input of ADC. The datasheet doesn't really say whether it will cap the data value to max or min when over range occur.  Please advise if the device will automatically saturate to all 1's for max or 0's for min.

While the datasheet show an expected error a clock after over range flag to at most 25%, is there any indication whether the lower or upper bound was in violation?

As a follow-on question in relates to Reset and Clock, if we decided it is necessary to perform a reset to the system (ADC), and the reset line is driven in such a way that it is a multiple of 8x input clock pulse, aligned with the CLKINP/N (@ 300 Mhz) in single bus mode.

I was informed from testbench result that the clock remain free running during reset, but would like to understand further on the expected behavior of CLKCOUT.

We plan to periodically issue a reset every 1/3 of a second when performing FFT elsewhere on board.

Upon reset, will ADS5400 momentarily use the default divider from register setting and/or possibly introduce a slight distortion to the clock?

How much more alignment effort will the ADS5400 perform based on the incoming reset to the free running input clock to maintain a continuous free running divided by 2 clock?   Will dramatic board temperature affect the reset point and cause a glitch during and immediately coming out of the 7-cycle latency?

Thanks much for any comment and feedback!

  • 0
    TI__Mastermind 29220 points

    Hi,

    The sample output will saturate at all 'one' or all 'zero' while in an over-range condition.  And for the over range flag, there is no indication made as to whether the over range is out of bounds on the upper or lower end of full scale.

    The reset input will reset the clock dividers that generate the output clocks.  in single bus mode this output clock is divided by two from the sample clock while in dual bus mode this is divided by four.  Either way the clock dividers are reset to a known phase relationship.   Figures 1, 2 and 3 in the datasheet attempt to show how the reset affects the output clock.   If the reset pulse comes along in a position such that it resets the output clock phase to be in a phase that it was going to be in anyway then the reset pulse does not cause a disturbance in the output clock.   For example, if the output clock is sample clock divide by two, and the reset comes along every 8 clock periods, then the output clock is not disturbed because the reset pulsecomes along on the same phase of the output clock each time.   But if there was a reset pulse 7 sample clocks after the last reset then the clock divider gets reset to a different position than it was going to be in without the reset.    Andas the figures try to show, if the clock dividers do get reset, the clock period of the output clock is always stretched - never a short cycle or runt cycle of the clock.  (This is particulary relevant to the clock/4 case - not so much for single bus mode)

    So if your periodic reset is something that is counted down from the sample clock and is always an even number of sample clocks, then output clock is not disturbed.  If the periodic reset does not have any relationship to sample clock, then sometimes the output clock would shift phase.

    The figures 1,2 3 show the reset pulse as a single pulse on one edge of sample clock, for clarity, but it need not be just a single cycle pulse.  I do not recall if a longer pulse of reset will hold the dividers in reset until reset goes inactive, or if only the rising edge of reset is looked at and the length of reset doesn't matter.  I think the device only looks for the low to high position of reset and doesn't care if the pulse itself is a number of cycles long.

    The reset input to the clock dividers is just digital logic, and its behavior is expected to be consistent across operating conditions.

    Regards,

    Richard P.

     

  • 0 in reply to Richard Prentice
    Prodigy 20 points
    Richard,

    Thank you so much for the thorough reply and precise interpretation of the datasheet.

    Normally I will not be overly concerned, but there are various factors involved in our reset mechanism that any shift to the clock can be problematic.

    You mentioned: "So if your periodic reset is something that is counted down from the sample clock and is always an even number of sample clocks, then output clock is not disturbed. If the periodic reset does not have any relationship to sample clock, then sometimes the output clock would shift phase."

    As an example where the clock and reset goes thru a bit of complicated scheme. Assume for ADC input clock, we use 37.5 Mhz to create 300 Mhz, phased aligned and fed 300 Mhz to the ADS5400 thru external cable. Reset signal is also fed externally thru cable, re-clocked by 37.5 Mhz that's coming from a separate cable. And we have a way to tune reset/37.5 Mhz and 300 Mhz thru a delay circuit as another chance to align and created an ideally synchronized relationship. I am just visioning any PLL tracking between the 37.5 Mhz and 300 Mhz would still create minimal back and forth shift, and we might observe that shift at the output of the ADS 5400 device when performing periodic reset.

    As part of the datapath, the ADS5400 output clock is to be used to operate DSP processing, bus interface and gigabit transceivers, and couple of other remote boards thru cabling with more gigabit transceivers. So potentially, the overall jitter in our operating conditions may quickly amplifying the divided by 2 clock from ADS5400, and path that adapt PLL (used by memory controller, gigabit transceiver) may momentarily lose lock.

    Given the example, I am perhaps really interested to find out how much jitter will the ADS5400 tolerate against the reset line.

    The simple solution I can think of would be to take the 300 Mhz and generate 150 Mhz ourselves, while using output clock only for latching the ADC data lines.

    Jeng