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dac37j82 DACCLK input

Berlauber
Intellectual 260 points
Other Parts Discussed in Thread: LMK04828, LMK04616

Hello,

DACCLKP/N input requirments are 0.5V common-mode and 800mV differential peak-to-peak, so I would like to know the reason of the decoupling capacitor of Figure 75 in the datasheet that removes the common-mode input voltage.

thank you!

  • 0
    TI__Genius 17290 points

    Hi,

    The DACCLK input self-biases to the correct common mode voltage. The DC blocking caps allow the clock driver and the DACCLK input to bias to their respective common mode voltages. LVPECL has a much higher common mode voltage, closer to 2V.

    Regards,
    Matt Guibord

  • 0 in reply to Matt Guibord
    Prodigy 100 points

    HI Matt

    Can the SYSREF and the DACCLK Vcom be externally DC Biased to higher voltages? How high and how can Vcom safely be driven? Perhaps there is a more detailed equivalent circuit for this that includes the internal bias on these pins?

    We have a case where we would like to DC couple the SYSREF and make the DACCLK coupling identical.

    Figure 75 in the data sheet (AC coupled example) shows the receiver equivalent circuit as a floating 100 Ohm differential termination and Vcom specification is 0.5V typical but no min or max?

    On the eval board where SYSREF appears to be DC coupled,  Vcom looks more like upwards of 0.55V than 0.5V?

    Like the eval board, to DC couple SYSREF, we would use a voltage divider, which also divides the signal amplitude.

    How high can we safely go on Vcom so we can maximize the signal?


    Thanks Dave

  • 0 in reply to Dave Lewis93983
    Prodigy 70 points

    Dave Lewis93983 said:

    HI Matt

    Can the SYSREF and the DACCLK Vcom be externally DC Biased to higher voltages? How high and how can Vcom safely be driven? Perhaps there is a more detailed equivalent circuit for this that includes the internal bias on these pins?

    We have a case where we would like to DC couple the SYSREF and make the DACCLK coupling identical.

    Figure 75 in the data sheet (AC coupled example) shows the receiver equivalent circuit as a floating 100 Ohm differential termination and Vcom specification is 0.5V typical but no min or max?

    On the eval board where SYSREF appears to be DC coupled,  Vcom looks more like upwards of 0.55V than 0.5V?

    Like the eval board, to DC couple SYSREF, we would use a voltage divider, which also divides the signal amplitude.

    How high can we safely go on Vcom so we can maximize the signal?


    Thanks Dave

    Hi,

    I have the exact same issue ! How can the datasheet mention the LVPECL standard, if the internal common mode voltage of the SYSREF pins are 0.5V ?

    Does it mean it is impossible to implement a LVPECL DC coupled communication for the SYSREF signal ? Because that's what i planned in my application, and I'm worrying about this datasheet's value atm ...

    Thanks,

    Alexis

  • 0 in reply to Alexis T
    TI__Guru* 91947 points

    Alexis,

    For DC coupling you will have to use either the LCPECL feature of the LMK04828 or HSDS 6mA feature of the LMK04616.

     

    LVPECL standard always calls for AC coupled, never DC coupled.

     

    Regards,

     

    Jim