• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 47 subscribers
  • Views 631 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS5407 Test Pattern Configuration

Mircea Bogdan
Intellectual 370 points
Other Parts Discussed in Thread: ADS5407

Hello,

I have 4 pieces  ADS5407 connected to an Altera FPGA. They seem to work well converting analog inputs.


Using the 3-pin SPI, I try to enable the test pattern mode.

Writing and reading to/from registers 3C and 3D works well, but register 3E reads back FFFF, no matter what I write.

Note that I can have the ADS5407s output all 0s, by writing 0x8000 to register 0x3C, but I can't make them toggle any pattern.

I do set HP1=0 (Addr 0x01, D01) before all this.

Is there something I'm missing here?

Thanks,

Mircea

  • 0
    TI__Genius 12965 points

    Mircea,

    The apps engineer is out of office at this time but will be able to respond next week.

    Ken.

  • 0 in reply to Ken C
    TI__Mastermind 29220 points

    Hi,

    I just set up the EVM on our bench and set the custom patterns.  Please see attached for the screenshots of the EVM SPI GUI setting up for alternating patterns (AAA and 555), a screenshot of the HSDCPro capturing that pattern, and a log of the SPI writes to set up for that.

    I don't see any problem writing to and reading from register 3E.  And I do see the patterns in the captured data.

    I don't see a problem with your description of the setup.  I also use 3-wire SPI mode in the EVM SPI GUI.  But i have just one ADC in use.   If you are able to see the outputs all zero after enabling the custom pattern mode by writing to 3C, then it would appear that you are able to do SPI writes and that the address and data don't have some format issues such as flipped order or such.   In your design, do you bus the SPI CLK to the four ADCs on a single signal (should be fine to do that) while driving a separate SPI ENABLE to each ADC?  And the third wire for data - it is a single signal bussed to all four ADCs or four separate signals?   Still - I can think of no reason why some SPI addresses let you write to and read from while some do not.   If multiple ADCs were driving the data line so that the data were corrupted, that would be the case for all ADCs i would think, not just some addresses.  If you had a formatting error such as getting the address order flipped from lsb to msb,  then some addresses might take a write and give a read-back if there happened to be a register at that wrong address, while other addresses would not return a value because there would be no register at that location.  But by being able to set the custom pattern enable bit, it doesn't seem to be that.

    I will need more information about your setup to begin to try to figure it out.ADS5402 Custom Patt.zip

    Regards,

    Richard P.

  • 0 in reply to Richard Prentice
    Intellectual 370 points

    Hi Richard,

    You are right, and I just found the firmware problem that was causing this issue.

    It works well now.

    Thanks,

    Mircea

  • 0 in reply to Mircea Bogdan
    Intellectual 370 points
    Hi Richard,
    I also have some questions about the Idle Channel Noise for ADS5407 for my particular application.
    Can you, please, contact me via email?
    Thanks,
    Mircea
  • 0 in reply to Mircea Bogdan
    TI__Mastermind 29220 points
    Hi,
    Sure. What is your email address? I don't have access to look it up through your TI account.
    Regards,Richard P.
  • 0 in reply to Richard Prentice
    Intellectual 370 points
    HI Richard,
    It's
    bogdan@edg.uchicago.edu
    Please, send me an email.
    Thanks,
    Mircea