Verilog source code for TSW1200 + ADS6445

Hi Richard,

Would you please send me the Verilog code for the TSW1200 + ADS6445 serial 2 wire LVDS,

if you have the Xilinx ISE project file, including timing constraint file, it would be perfect.

I am designing ADS6445 based digitizer, try to understand the how to timing constraint the ADC interface?

my email:  stinver@gmail.com

Many thanks

STinver