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ADC12D1600RF

What is TI's current position on DESCLKIQ?  Is this a mode I can get working?  Looking at TIDU175 and 0451.TI, "Board G" looks like a pretty good design.


Why does the results table between these two documents differ?

It seems like the main concern with DESCLKIQ is the interleaving spur.  The document says you can calibrate it to -35 dBFS.  It seems like this spur should be relative to the input signal power.  Is this correct?  So if my input signal is at -35 dBFS, the interleaving spur is at about -70 dBFS.

  • Also, TIDU175 shows a block diagram with a track and hold in front of 4 ADCs. Does TI have a reference design for this configuration? What parts are recommended for it??
  • Hi Dan,

    The results shown in TIDU175 are different than (0451) document because in course of doing the TI design more in-depth analysis was done. So I would recommend following the results shown in the TIDU175.

    Yes, the gain mismatch and timing related interleaving spur is input amplitude dependent, so if the input signal is dropped by 35 dB the interleaving spur should also go down by similar amount.
    So if the spur was at -35dBFS at -0.5 dBFS input it should drop to around -70 dBFS with a -35dBFS input.

    Regards,
    Neeraj Gill
  • Hi Dan

    Unfortunately we do not have a reference design for that Track and Hold system shown in the diagram.

    Best regards,

    Jim B

  • Looking at TIDU175, Table 6 and Table 7 are identical. Could TIDU175 have a typographical error in it?
  • Bummer. Is there a PN for the track and hold IC in the picture, or is this a hypothetical part?
  • Hi Dan

    After some review it does appear that Table 7 is indeed a copy of Table 6. Thanks for pointing this out. 

    The Table 7 values in the other presentation are accurate, duplicated here:

    DESCLKIQ Criteria

    Board A

    Board C

    Board F

    Board G

    Dynamic Performance

    Below Average

    Not Recommended

    Average

    Average

    Insertion Loss

    Below Average

    Good

    Excellent

    Excellent

    Interleaving Spur Adjust

    Good

    Poor

    Average

    Average

    Multi-mode Application

    Average

    Excellent

    Average

    Average

    We'll get this TIDU document updated as soon as possible.

    Best regards,

    Jim B

  • Hi Dan

    The track and hold in the picture is a hypothetical part.

    Best regards,

    Jim B

  • Is it possible to get DESCLKIQ mode to work? 

    Based on the tables in TIDU175, a person would think that "circuit G" is the best.  But once you pick through the verbage, it sounds like circuit A is the only hope, because you can tune the interleaver spur down.  I suspect that the interleaver spur sets the SFDR, etc...

    What circuit would you try if you were going to design a DESCLKIQ card.

  • Hi Dan

    I would only use DESCLKIQ mode in the following cases:

    1. A high bandwidth time domain application where the errors due to the timing/gain interleaving mismatch are not important.
    2. An RF application with a very narrow input bandwidth, with the capability to apply an external test tone to allow calibration of the DES Timing and Gain settings to minimize the interleaving spur magnitude. This tuning will be valid over a limited frequency range.

    For all other cases I would recommend DESIQ mode where better I/Q input signal path matching is achieved.

    Best regards,

    Jim B